This is the 4.19.73 stable release
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Merge 4.19.73 into android-4.19
Changes in 4.19.73
ALSA: hda - Fix potential endless loop at applying quirks
ALSA: hda/realtek - Fix overridden device-specific initialization
ALSA: hda/realtek - Add quirk for HP Pavilion 15
ALSA: hda/realtek - Enable internal speaker & headset mic of ASUS UX431FL
ALSA: hda/realtek - Fix the problem of two front mics on a ThinkCentre
sched/fair: Don't assign runtime for throttled cfs_rq
drm/vmwgfx: Fix double free in vmw_recv_msg()
vhost/test: fix build for vhost test
vhost/test: fix build for vhost test - again
powerpc/tm: Fix FP/VMX unavailable exceptions inside a transaction
batman-adv: fix uninit-value in batadv_netlink_get_ifindex()
batman-adv: Only read OGM tvlv_len after buffer len check
hv_sock: Fix hang when a connection is closed
Blk-iolatency: warn on negative inflight IO counter
blk-iolatency: fix STS_AGAIN handling
{nl,mac}80211: fix interface combinations on crypto controlled devices
timekeeping: Use proper ktime_add when adding nsecs in coarse offset
selftests: fib_rule_tests: use pre-defined DEV_ADDR
x86/ftrace: Fix warning and considate ftrace_jmp_replace() and ftrace_call_replace()
powerpc/64: mark start_here_multiplatform as __ref
media: stm32-dcmi: fix irq = 0 case
arm64: dts: rockchip: enable usb-host regulators at boot on rk3328-rock64
scripts/decode_stacktrace: match basepath using shell prefix operator, not regex
riscv: remove unused variable in ftrace
nvme-fc: use separate work queue to avoid warning
clk: s2mps11: Add used attribute to s2mps11_dt_match
remoteproc: qcom: q6v5: shore up resource probe handling
modules: always page-align module section allocations
kernel/module: Fix mem leak in module_add_modinfo_attrs
drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"
media: cec/v4l2: move V4L2 specific CEC functions to V4L2
media: cec: remove cec-edid.c
scsi: qla2xxx: Move log messages before issuing command to firmware
keys: Fix the use of the C++ keyword "private" in uapi/linux/keyctl.h
Drivers: hv: kvp: Fix two "this statement may fall through" warnings
x86, hibernate: Fix nosave_regions setup for hibernation
remoteproc: qcom: q6v5-mss: add SCM probe dependency
drm/amdgpu/gfx9: Update gfx9 golden settings.
drm/amdgpu: Update gc_9_0 golden settings.
KVM: x86: hyperv: enforce vp_index < KVM_MAX_VCPUS
KVM: x86: hyperv: consistently use 'hv_vcpu' for 'struct kvm_vcpu_hv' variables
KVM: x86: hyperv: keep track of mismatched VP indexes
KVM: hyperv: define VP assist page helpers
x86/kvm/lapic: preserve gfn_to_hva_cache len on cache reinit
drm/i915: Fix intel_dp_mst_best_encoder()
drm/i915: Rename PLANE_CTL_DECOMPRESSION_ENABLE
drm/i915/gen9+: Fix initial readout for Y tiled framebuffers
drm/atomic_helper: Disallow new modesets on unregistered connectors
Drivers: hv: kvp: Fix the indentation of some "break" statements
Drivers: hv: kvp: Fix the recent regression caused by incorrect clean-up
powerplay: Respect units on max dcfclk watermark
drm/amd/pp: Fix truncated clock value when set watermark
drm/amd/dm: Understand why attaching path/tile properties are needed
ARM: davinci: da8xx: define gpio interrupts as separate resources
ARM: davinci: dm365: define gpio interrupts as separate resources
ARM: davinci: dm646x: define gpio interrupts as separate resources
ARM: davinci: dm355: define gpio interrupts as separate resources
ARM: davinci: dm644x: define gpio interrupts as separate resources
s390/zcrypt: reinit ap queue state machine during device probe
media: vim2m: use workqueue
media: vim2m: use cancel_delayed_work_sync instead of flush_schedule_work
drm/i915: Restore sane defaults for KMS on GEM error load
drm/i915: Cleanup gt powerstate from gem
KVM: PPC: Book3S HV: Fix race between kvm_unmap_hva_range and MMU mode switch
Btrfs: clean up scrub is_dev_replace parameter
Btrfs: fix deadlock with memory reclaim during scrub
btrfs: Remove extent_io_ops::fill_delalloc
btrfs: Fix error handling in btrfs_cleanup_ordered_extents
scsi: megaraid_sas: Fix combined reply queue mode detection
scsi: megaraid_sas: Add check for reset adapter bit
scsi: megaraid_sas: Use 63-bit DMA addressing
powerpc/pkeys: Fix handling of pkey state across fork()
btrfs: volumes: Make sure no dev extent is beyond device boundary
btrfs: Use real device structure to verify dev extent
media: vim2m: only cancel work if it is for right context
ARC: show_regs: lockdep: re-enable preemption
ARC: mm: do_page_fault fixes #1: relinquish mmap_sem if signal arrives while handle_mm_fault
IB/uverbs: Fix OOPs upon device disassociation
crypto: ccree - fix resume race condition on init
crypto: ccree - add missing inline qualifier
drm/vblank: Allow dynamic per-crtc max_vblank_count
drm/i915/ilk: Fix warning when reading emon_status with no output
mfd: Kconfig: Fix I2C_DESIGNWARE_PLATFORM dependencies
tpm: Fix some name collisions with drivers/char/tpm.h
bcache: replace hard coded number with BUCKET_GC_GEN_MAX
bcache: treat stale && dirty keys as bad keys
KVM: VMX: Compare only a single byte for VMCS' "launched" in vCPU-run
iio: adc: exynos-adc: Add S5PV210 variant
dt-bindings: iio: adc: exynos-adc: Add S5PV210 variant
iio: adc: exynos-adc: Use proper number of channels for Exynos4x12
mt76: fix corrupted software generated tx CCMP PN
drm/nouveau: Don't WARN_ON VCPI allocation failures
iwlwifi: fix devices with PCI Device ID 0x34F0 and 11ac RF modules
iwlwifi: add new card for 9260 series
x86/kvmclock: set offset for kvm unstable clock
spi: spi-gpio: fix SPI_CS_HIGH capability
powerpc/kvm: Save and restore host AMR/IAMR/UAMOR
mmc: renesas_sdhi: Fix card initialization failure in high speed mode
btrfs: scrub: pass fs_info to scrub_setup_ctx
btrfs: scrub: move scrub_setup_ctx allocation out of device_list_mutex
btrfs: scrub: fix circular locking dependency warning
btrfs: init csum_list before possible free
PCI: qcom: Fix error handling in runtime PM support
PCI: qcom: Don't deassert reset GPIO during probe
drm: add __user attribute to ptr_to_compat()
CIFS: Fix error paths in writeback code
CIFS: Fix leaking locked VFS cache pages in writeback retry
drm/i915: Handle vm_mmap error during I915_GEM_MMAP ioctl with WC set
drm/i915: Sanity check mmap length against object size
usb: typec: tcpm: Try PD-2.0 if sink does not respond to 3.0 source-caps
arm64: dts: stratix10: add the sysmgr-syscon property from the gmac's
IB/mlx5: Reset access mask when looping inside page fault handler
kvm: mmu: Fix overflow on kvm mmu page limit calculation
x86/kvm: move kvm_load/put_guest_xcr0 into atomic context
KVM: x86: Always use 32-bit SMRAM save state for 32-bit kernels
cifs: Fix lease buffer length error
media: i2c: tda1997x: select V4L2_FWNODE
ext4: protect journal inode's blocks using block_validity
ARM: dts: qcom: ipq4019: fix PCI range
ARM: dts: qcom: ipq4019: Fix MSI IRQ type
ARM: dts: qcom: ipq4019: enlarge PCIe BAR range
dt-bindings: mmc: Add supports-cqe property
dt-bindings: mmc: Add disable-cqe-dcmd property.
PCI: Add macro for Switchtec quirk declarations
PCI: Reset Lenovo ThinkPad P50 nvgpu at boot if necessary
dm mpath: fix missing call of path selector type->end_io
blk-mq: free hw queue's resource in hctx's release handler
mmc: sdhci-pci: Add support for Intel CML
PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify code
cifs: smbd: take an array of reqeusts when sending upper layer data
dm crypt: move detailed message into debug level
signal/arc: Use force_sig_fault where appropriate
ARC: mm: fix uninitialised signal code in do_page_fault
ARC: mm: SIGSEGV userspace trying to access kernel virtual memory
drm/amdkfd: Add missing Polaris10 ID
kvm: Check irqchip mode before assign irqfd
drm/amdgpu: fix ring test failure issue during s3 in vce 3.0 (V2)
drm/amdgpu/{uvd,vcn}: fetch ring's read_ptr after alloc
Btrfs: fix race between block group removal and block group allocation
cifs: add spinlock for the openFileList to cifsInodeInfo
clk: tegra: Fix maximum audio sync clock for Tegra124/210
clk: tegra210: Fix default rates for HDA clocks
IB/hfi1: Avoid hardlockup with flushlist_lock
apparmor: reset pos on failure to unpack for various functions
scsi: target/core: Use the SECTOR_SHIFT constant
scsi: target/iblock: Fix overrun in WRITE SAME emulation
staging: wilc1000: fix error path cleanup in wilc_wlan_initialize()
scsi: zfcp: fix request object use-after-free in send path causing wrong traces
cifs: Properly handle auto disabling of serverino option
ALSA: hda - Don't resume forcibly i915 HDMI/DP codec
ceph: use ceph_evict_inode to cleanup inode's resource
KVM: x86: optimize check for valid PAT value
KVM: VMX: Always signal #GP on WRMSR to MSR_IA32_CR_PAT with bad value
KVM: VMX: Fix handling of #MC that occurs during VM-Entry
KVM: VMX: check CPUID before allowing read/write of IA32_XSS
KVM: PPC: Use ccr field in pt_regs struct embedded in vcpu struct
KVM: PPC: Book3S HV: Fix CR0 setting in TM emulation
ARM: dts: gemini: Set DIR-685 SPI CS as active low
RDMA/srp: Document srp_parse_in() arguments
RDMA/srp: Accept again source addresses that do not have a port number
btrfs: correctly validate compression type
resource: Include resource end in walk_*() interfaces
resource: Fix find_next_iomem_res() iteration issue
resource: fix locking in find_next_iomem_res()
pstore: Fix double-free in pstore_mkfile() failure path
dm thin metadata: check if in fail_io mode when setting needs_check
drm/panel: Add support for Armadeus ST0700 Adapt
ALSA: hda - Fix intermittent CORB/RIRB stall on Intel chips
powerpc/mm: Limit rma_size to 1TB when running without HV mode
iommu/iova: Remove stale cached32_node
gpio: don't WARN() on NULL descs if gpiolib is disabled
i2c: at91: disable TXRDY interrupt after sending data
i2c: at91: fix clk_offset for sama5d2
mm/migrate.c: initialize pud_entry in migrate_vma()
iio: adc: gyroadc: fix uninitialized return code
NFSv4: Fix delegation state recovery
bcache: only clear BTREE_NODE_dirty bit when it is set
bcache: add comments for mutex_lock(&b->write_lock)
bcache: fix race in btree_flush_write()
drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV
virtio/s390: fix race on airq_areas[]
drm/atomic_helper: Allow DPMS On<->Off changes for unregistered connectors
ext4: don't perform block validity checks on the journal inode
ext4: fix block validity checks for journal inodes using indirect blocks
ext4: unsigned int compared against zero
PCI: Reset both NVIDIA GPU and HDA in ThinkPad P50 workaround
powerpc/tm: Remove msr_tm_active()
powerpc/tm: Fix restoring FP/VMX facility incorrectly on interrupts
vhost: make sure log_num < in_num
Linux 4.19.73
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I7bc57825aeb36759bb8e8726888da9af06392c09
This commit is contained in:
Greg Kroah-Hartman
commit
8ca5759502
@ -0,0 +1,9 @@
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Armadeus ST0700 Adapt. A Santek ST0700I5Y-RBSLW 7.0" WVGA (800x480) TFT with
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an adapter board.
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Required properties:
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- compatible: "armadeus,st0700-adapt"
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- power-supply: see panel-common.txt
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Optional properties:
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- backlight: see panel-common.txt
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@ -11,11 +11,13 @@ New driver handles the following
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Required properties:
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- compatible: Must be "samsung,exynos-adc-v1"
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for exynos4412/5250 and s5pv210 controllers.
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for Exynos5250 controllers.
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Must be "samsung,exynos-adc-v2" for
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future controllers.
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Must be "samsung,exynos3250-adc" for
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controllers compatible with ADC of Exynos3250.
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Must be "samsung,exynos4212-adc" for
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controllers compatible with ADC of Exynos4212 and Exynos4412.
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Must be "samsung,exynos7-adc" for
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the ADC in Exynos7 and compatibles
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Must be "samsung,s3c2410-adc" for
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@ -28,6 +30,8 @@ Required properties:
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the ADC in s3c2443 and compatibles
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Must be "samsung,s3c6410-adc" for
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the ADC in s3c6410 and compatibles
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Must be "samsung,s5pv210-adc" for
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the ADC in s5pv210 and compatibles
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- reg: List of ADC register address range
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- The base address and range of ADC register
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- The base address and range of ADC_PHY register (every
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@ -62,6 +62,10 @@ Optional properties:
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be referred to mmc-pwrseq-simple.txt. But now it's reused as a tunable delay
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waiting for I/O signalling and card power supply to be stable, regardless of
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whether pwrseq-simple is used. Default to 10ms if no available.
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- supports-cqe : The presence of this property indicates that the corresponding
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MMC host controller supports HW command queue feature.
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- disable-cqe-dcmd: This property indicates that the MMC controller's command
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queue engine (CQE) does not support direct commands (DCMDs).
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*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
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polarity properties, we have to fix the meaning of the "normal" and "inverted"
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2
Makefile
2
Makefile
@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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VERSION = 4
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PATCHLEVEL = 19
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SUBLEVEL = 72
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SUBLEVEL = 73
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EXTRAVERSION =
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NAME = "People's Front"
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@ -179,6 +179,12 @@ void show_regs(struct pt_regs *regs)
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struct task_struct *tsk = current;
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struct callee_regs *cregs;
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/*
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* generic code calls us with preemption disabled, but some calls
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* here could sleep, so re-enable to avoid lockdep splat
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*/
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preempt_enable();
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print_task_path_n_nm(tsk);
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show_regs_print_info(KERN_INFO);
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@ -221,6 +227,8 @@ void show_regs(struct pt_regs *regs)
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cregs = (struct callee_regs *)current->thread.callee_reg;
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if (cregs)
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show_callee_regs(cregs);
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preempt_disable();
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}
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void show_kernel_fault_diag(const char *str, struct pt_regs *regs,
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@ -66,14 +66,12 @@ void do_page_fault(unsigned long address, struct pt_regs *regs)
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struct vm_area_struct *vma = NULL;
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struct task_struct *tsk = current;
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struct mm_struct *mm = tsk->mm;
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siginfo_t info;
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int si_code = SEGV_MAPERR;
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int ret;
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vm_fault_t fault;
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int write = regs->ecr_cause & ECR_C_PROTV_STORE; /* ST/EX */
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unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
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clear_siginfo(&info);
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/*
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* We fault-in kernel-space virtual memory on-demand. The
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* 'reference' page table is init_mm.pgd.
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@ -83,16 +81,14 @@ void do_page_fault(unsigned long address, struct pt_regs *regs)
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* only copy the information from the master page table,
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* nothing more.
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*/
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if (address >= VMALLOC_START) {
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if (address >= VMALLOC_START && !user_mode(regs)) {
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ret = handle_kernel_vaddr_fault(address);
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if (unlikely(ret))
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goto bad_area_nosemaphore;
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goto no_context;
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else
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return;
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}
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info.si_code = SEGV_MAPERR;
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/*
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* If we're in an interrupt or have no user
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* context, we must not take the fault..
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@ -119,7 +115,7 @@ retry:
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* we can handle it..
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*/
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good_area:
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info.si_code = SEGV_ACCERR;
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si_code = SEGV_ACCERR;
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/* Handle protection violation, execute on heap or stack */
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@ -143,12 +139,17 @@ good_area:
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*/
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fault = handle_mm_fault(vma, address, flags);
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/* If Pagefault was interrupted by SIGKILL, exit page fault "early" */
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if (unlikely(fatal_signal_pending(current))) {
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if ((fault & VM_FAULT_ERROR) && !(fault & VM_FAULT_RETRY))
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up_read(&mm->mmap_sem);
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if (user_mode(regs))
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/*
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* if fault retry, mmap_sem already relinquished by core mm
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* so OK to return to user mode (with signal handled first)
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*/
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if (fault & VM_FAULT_RETRY) {
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if (!user_mode(regs))
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goto no_context;
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return;
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}
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}
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perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
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@ -195,15 +196,10 @@ good_area:
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bad_area:
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up_read(&mm->mmap_sem);
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bad_area_nosemaphore:
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/* User mode accesses just cause a SIGSEGV */
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if (user_mode(regs)) {
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tsk->thread.fault_address = address;
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info.si_signo = SIGSEGV;
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info.si_errno = 0;
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/* info.si_code has been set above */
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info.si_addr = (void __user *)address;
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force_sig_info(SIGSEGV, &info, tsk);
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force_sig_fault(SIGSEGV, si_code, (void __user *)address, tsk);
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return;
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}
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@ -238,9 +234,5 @@ do_sigbus:
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goto no_context;
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tsk->thread.fault_address = address;
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info.si_signo = SIGBUS;
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info.si_errno = 0;
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info.si_code = BUS_ADRERR;
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info.si_addr = (void __user *)address;
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force_sig_info(SIGBUS, &info, tsk);
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force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)address, tsk);
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}
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@ -65,7 +65,7 @@
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gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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/* Collides with pflash CE1, not so cool */
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cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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num-chipselects = <1>;
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panel: display@0 {
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@ -386,10 +386,10 @@
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
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0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
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ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
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<0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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@ -704,6 +704,46 @@ static struct resource da8xx_gpio_resources[] = {
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},
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{ /* interrupt */
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.start = IRQ_DA8XX_GPIO0,
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.end = IRQ_DA8XX_GPIO0,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_DA8XX_GPIO1,
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.end = IRQ_DA8XX_GPIO1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_DA8XX_GPIO2,
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.end = IRQ_DA8XX_GPIO2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_GPIO3,
|
||||
.end = IRQ_DA8XX_GPIO3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_GPIO4,
|
||||
.end = IRQ_DA8XX_GPIO4,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_GPIO5,
|
||||
.end = IRQ_DA8XX_GPIO5,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_GPIO6,
|
||||
.end = IRQ_DA8XX_GPIO6,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_GPIO7,
|
||||
.end = IRQ_DA8XX_GPIO7,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DA8XX_GPIO8,
|
||||
.end = IRQ_DA8XX_GPIO8,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
||||
@ -548,6 +548,36 @@ static struct resource dm355_gpio_resources[] = {
|
||||
},
|
||||
{ /* interrupt */
|
||||
.start = IRQ_DM355_GPIOBNK0,
|
||||
.end = IRQ_DM355_GPIOBNK0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM355_GPIOBNK1,
|
||||
.end = IRQ_DM355_GPIOBNK1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM355_GPIOBNK2,
|
||||
.end = IRQ_DM355_GPIOBNK2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM355_GPIOBNK3,
|
||||
.end = IRQ_DM355_GPIOBNK3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM355_GPIOBNK4,
|
||||
.end = IRQ_DM355_GPIOBNK4,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM355_GPIOBNK5,
|
||||
.end = IRQ_DM355_GPIOBNK5,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM355_GPIOBNK6,
|
||||
.end = IRQ_DM355_GPIOBNK6,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
||||
@ -267,6 +267,41 @@ static struct resource dm365_gpio_resources[] = {
|
||||
},
|
||||
{ /* interrupt */
|
||||
.start = IRQ_DM365_GPIO0,
|
||||
.end = IRQ_DM365_GPIO0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM365_GPIO1,
|
||||
.end = IRQ_DM365_GPIO1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM365_GPIO2,
|
||||
.end = IRQ_DM365_GPIO2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM365_GPIO3,
|
||||
.end = IRQ_DM365_GPIO3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM365_GPIO4,
|
||||
.end = IRQ_DM365_GPIO4,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM365_GPIO5,
|
||||
.end = IRQ_DM365_GPIO5,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM365_GPIO6,
|
||||
.end = IRQ_DM365_GPIO6,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM365_GPIO7,
|
||||
.end = IRQ_DM365_GPIO7,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
||||
@ -492,6 +492,26 @@ static struct resource dm644_gpio_resources[] = {
|
||||
},
|
||||
{ /* interrupt */
|
||||
.start = IRQ_GPIOBNK0,
|
||||
.end = IRQ_GPIOBNK0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_GPIOBNK1,
|
||||
.end = IRQ_GPIOBNK1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_GPIOBNK2,
|
||||
.end = IRQ_GPIOBNK2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_GPIOBNK3,
|
||||
.end = IRQ_GPIOBNK3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_GPIOBNK4,
|
||||
.end = IRQ_GPIOBNK4,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
||||
@ -442,6 +442,16 @@ static struct resource dm646x_gpio_resources[] = {
|
||||
},
|
||||
{ /* interrupt */
|
||||
.start = IRQ_DM646X_GPIOBNK0,
|
||||
.end = IRQ_DM646X_GPIOBNK0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM646X_GPIOBNK1,
|
||||
.end = IRQ_DM646X_GPIOBNK1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM646X_GPIOBNK2,
|
||||
.end = IRQ_DM646X_GPIOBNK2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
||||
@ -140,6 +140,7 @@
|
||||
tx-fifo-depth = <16384>;
|
||||
rx-fifo-depth = <16384>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -156,6 +157,7 @@
|
||||
tx-fifo-depth = <16384>;
|
||||
rx-fifo-depth = <16384>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
altr,sysmgr-syscon = <&sysmgr 0x48 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -172,6 +174,7 @@
|
||||
tx-fifo-depth = <16384>;
|
||||
rx-fifo-depth = <16384>;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -40,6 +40,7 @@
|
||||
pinctrl-0 = <&usb30_host_drv>;
|
||||
regulator-name = "vcc_host_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
@ -50,6 +51,7 @@
|
||||
pinctrl-0 = <&usb20_host_drv>;
|
||||
regulator-name = "vcc_host1_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
|
||||
@ -301,12 +301,12 @@ static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num)
|
||||
|
||||
static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val)
|
||||
{
|
||||
vcpu->arch.cr = val;
|
||||
vcpu->arch.regs.ccr = val;
|
||||
}
|
||||
|
||||
static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return vcpu->arch.cr;
|
||||
return vcpu->arch.regs.ccr;
|
||||
}
|
||||
|
||||
static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, ulong val)
|
||||
|
||||
@ -482,7 +482,7 @@ static inline u64 sanitize_msr(u64 msr)
|
||||
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||||
static inline void copy_from_checkpoint(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
vcpu->arch.cr = vcpu->arch.cr_tm;
|
||||
vcpu->arch.regs.ccr = vcpu->arch.cr_tm;
|
||||
vcpu->arch.regs.xer = vcpu->arch.xer_tm;
|
||||
vcpu->arch.regs.link = vcpu->arch.lr_tm;
|
||||
vcpu->arch.regs.ctr = vcpu->arch.ctr_tm;
|
||||
@ -499,7 +499,7 @@ static inline void copy_from_checkpoint(struct kvm_vcpu *vcpu)
|
||||
|
||||
static inline void copy_to_checkpoint(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
vcpu->arch.cr_tm = vcpu->arch.cr;
|
||||
vcpu->arch.cr_tm = vcpu->arch.regs.ccr;
|
||||
vcpu->arch.xer_tm = vcpu->arch.regs.xer;
|
||||
vcpu->arch.lr_tm = vcpu->arch.regs.link;
|
||||
vcpu->arch.ctr_tm = vcpu->arch.regs.ctr;
|
||||
|
||||
@ -46,12 +46,12 @@ static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num)
|
||||
|
||||
static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val)
|
||||
{
|
||||
vcpu->arch.cr = val;
|
||||
vcpu->arch.regs.ccr = val;
|
||||
}
|
||||
|
||||
static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return vcpu->arch.cr;
|
||||
return vcpu->arch.regs.ccr;
|
||||
}
|
||||
|
||||
static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, ulong val)
|
||||
|
||||
@ -538,8 +538,6 @@ struct kvm_vcpu_arch {
|
||||
ulong tar;
|
||||
#endif
|
||||
|
||||
u32 cr;
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3S
|
||||
ulong hflags;
|
||||
ulong guest_owned_ext;
|
||||
|
||||
@ -217,12 +217,6 @@ static inline void enter_lazy_tlb(struct mm_struct *mm,
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline int arch_dup_mmap(struct mm_struct *oldmm,
|
||||
struct mm_struct *mm)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_PPC_BOOK3S_64
|
||||
static inline void arch_exit_mmap(struct mm_struct *mm)
|
||||
{
|
||||
@ -247,6 +241,7 @@ static inline void arch_bprm_mm_init(struct mm_struct *mm,
|
||||
#ifdef CONFIG_PPC_MEM_KEYS
|
||||
bool arch_vma_access_permitted(struct vm_area_struct *vma, bool write,
|
||||
bool execute, bool foreign);
|
||||
void arch_dup_pkeys(struct mm_struct *oldmm, struct mm_struct *mm);
|
||||
#else /* CONFIG_PPC_MEM_KEYS */
|
||||
static inline bool arch_vma_access_permitted(struct vm_area_struct *vma,
|
||||
bool write, bool execute, bool foreign)
|
||||
@ -259,6 +254,7 @@ static inline bool arch_vma_access_permitted(struct vm_area_struct *vma,
|
||||
#define thread_pkey_regs_save(thread)
|
||||
#define thread_pkey_regs_restore(new_thread, old_thread)
|
||||
#define thread_pkey_regs_init(thread)
|
||||
#define arch_dup_pkeys(oldmm, mm)
|
||||
|
||||
static inline u64 pte_to_hpte_pkey_bits(u64 pteflags)
|
||||
{
|
||||
@ -267,5 +263,12 @@ static inline u64 pte_to_hpte_pkey_bits(u64 pteflags)
|
||||
|
||||
#endif /* CONFIG_PPC_MEM_KEYS */
|
||||
|
||||
static inline int arch_dup_mmap(struct mm_struct *oldmm,
|
||||
struct mm_struct *mm)
|
||||
{
|
||||
arch_dup_pkeys(oldmm, mm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASM_POWERPC_MMU_CONTEXT_H */
|
||||
|
||||
@ -118,11 +118,16 @@
|
||||
#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
|
||||
#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
|
||||
#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S) /* Transaction State bits */
|
||||
#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
|
||||
#define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
|
||||
#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
|
||||
#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
|
||||
|
||||
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||||
#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
|
||||
#else
|
||||
#define MSR_TM_ACTIVE(x) 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PPC_BOOK3S_64)
|
||||
#define MSR_64BIT MSR_SF
|
||||
|
||||
|
||||
@ -438,7 +438,7 @@ int main(void)
|
||||
#ifdef CONFIG_PPC_BOOK3S
|
||||
OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
|
||||
#endif
|
||||
OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
|
||||
OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
|
||||
OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
|
||||
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
|
||||
OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
|
||||
@ -695,7 +695,7 @@ int main(void)
|
||||
#endif /* CONFIG_PPC_BOOK3S_64 */
|
||||
|
||||
#else /* CONFIG_PPC_BOOK3S */
|
||||
OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
|
||||
OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
|
||||
OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
|
||||
OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
|
||||
OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
|
||||
|
||||
@ -906,6 +906,7 @@ p_toc: .8byte __toc_start + 0x8000 - 0b
|
||||
/*
|
||||
* This is where the main kernel code starts.
|
||||
*/
|
||||
__REF
|
||||
start_here_multiplatform:
|
||||
/* set up the TOC */
|
||||
bl relative_toc
|
||||
@ -981,6 +982,7 @@ start_here_multiplatform:
|
||||
RFI
|
||||
b . /* prevent speculative execution */
|
||||
|
||||
.previous
|
||||
/* This is where all platforms converge execution */
|
||||
|
||||
start_here_common:
|
||||
|
||||
@ -102,27 +102,8 @@ static void check_if_tm_restore_required(struct task_struct *tsk)
|
||||
}
|
||||
}
|
||||
|
||||
static inline bool msr_tm_active(unsigned long msr)
|
||||
{
|
||||
return MSR_TM_ACTIVE(msr);
|
||||
}
|
||||
|
||||
static bool tm_active_with_fp(struct task_struct *tsk)
|
||||
{
|
||||
return msr_tm_active(tsk->thread.regs->msr) &&
|
||||
(tsk->thread.ckpt_regs.msr & MSR_FP);
|
||||
}
|
||||
|
||||
static bool tm_active_with_altivec(struct task_struct *tsk)
|
||||
{
|
||||
return msr_tm_active(tsk->thread.regs->msr) &&
|
||||
(tsk->thread.ckpt_regs.msr & MSR_VEC);
|
||||
}
|
||||
#else
|
||||
static inline bool msr_tm_active(unsigned long msr) { return false; }
|
||||
static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
|
||||
static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; }
|
||||
static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; }
|
||||
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
|
||||
|
||||
bool strict_msr_control;
|
||||
@ -247,7 +228,8 @@ void enable_kernel_fp(void)
|
||||
* giveup as this would save to the 'live' structure not the
|
||||
* checkpointed structure.
|
||||
*/
|
||||
if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
|
||||
if (!MSR_TM_ACTIVE(cpumsr) &&
|
||||
MSR_TM_ACTIVE(current->thread.regs->msr))
|
||||
return;
|
||||
__giveup_fpu(current);
|
||||
}
|
||||
@ -256,7 +238,7 @@ EXPORT_SYMBOL(enable_kernel_fp);
|
||||
|
||||
static int restore_fp(struct task_struct *tsk)
|
||||
{
|
||||
if (tsk->thread.load_fp || tm_active_with_fp(tsk)) {
|
||||
if (tsk->thread.load_fp) {
|
||||
load_fp_state(¤t->thread.fp_state);
|
||||
current->thread.load_fp++;
|
||||
return 1;
|
||||
@ -311,7 +293,8 @@ void enable_kernel_altivec(void)
|
||||
* giveup as this would save to the 'live' structure not the
|
||||
* checkpointed structure.
|
||||
*/
|
||||
if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
|
||||
if (!MSR_TM_ACTIVE(cpumsr) &&
|
||||
MSR_TM_ACTIVE(current->thread.regs->msr))
|
||||
return;
|
||||
__giveup_altivec(current);
|
||||
}
|
||||
@ -337,8 +320,7 @@ EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
|
||||
|
||||
static int restore_altivec(struct task_struct *tsk)
|
||||
{
|
||||
if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
|
||||
(tsk->thread.load_vec || tm_active_with_altivec(tsk))) {
|
||||
if (cpu_has_feature(CPU_FTR_ALTIVEC) && (tsk->thread.load_vec)) {
|
||||
load_vr_state(&tsk->thread.vr_state);
|
||||
tsk->thread.used_vr = 1;
|
||||
tsk->thread.load_vec++;
|
||||
@ -397,7 +379,8 @@ void enable_kernel_vsx(void)
|
||||
* giveup as this would save to the 'live' structure not the
|
||||
* checkpointed structure.
|
||||
*/
|
||||
if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
|
||||
if (!MSR_TM_ACTIVE(cpumsr) &&
|
||||
MSR_TM_ACTIVE(current->thread.regs->msr))
|
||||
return;
|
||||
__giveup_vsx(current);
|
||||
}
|
||||
@ -499,13 +482,14 @@ void giveup_all(struct task_struct *tsk)
|
||||
if (!tsk->thread.regs)
|
||||
return;
|
||||
|
||||
check_if_tm_restore_required(tsk);
|
||||
|
||||
usermsr = tsk->thread.regs->msr;
|
||||
|
||||
if ((usermsr & msr_all_available) == 0)
|
||||
return;
|
||||
|
||||
msr_check_and_set(msr_all_available);
|
||||
check_if_tm_restore_required(tsk);
|
||||
|
||||
WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
|
||||
|
||||
@ -530,7 +514,7 @@ void restore_math(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long msr;
|
||||
|
||||
if (!msr_tm_active(regs->msr) &&
|
||||
if (!MSR_TM_ACTIVE(regs->msr) &&
|
||||
!current->thread.load_fp && !loadvec(current->thread))
|
||||
return;
|
||||
|
||||
|
||||
@ -744,12 +744,15 @@ void kvmppc_rmap_reset(struct kvm *kvm)
|
||||
srcu_idx = srcu_read_lock(&kvm->srcu);
|
||||
slots = kvm_memslots(kvm);
|
||||
kvm_for_each_memslot(memslot, slots) {
|
||||
/* Mutual exclusion with kvm_unmap_hva_range etc. */
|
||||
spin_lock(&kvm->mmu_lock);
|
||||
/*
|
||||
* This assumes it is acceptable to lose reference and
|
||||
* change bits across a reset.
|
||||
*/
|
||||
memset(memslot->arch.rmap, 0,
|
||||
memslot->npages * sizeof(*memslot->arch.rmap));
|
||||
spin_unlock(&kvm->mmu_lock);
|
||||
}
|
||||
srcu_read_unlock(&kvm->srcu, srcu_idx);
|
||||
}
|
||||
|
||||
@ -110,7 +110,7 @@ static inline void kvmppc_copyto_vcpu_tm(struct kvm_vcpu *vcpu)
|
||||
vcpu->arch.ctr_tm = vcpu->arch.regs.ctr;
|
||||
vcpu->arch.tar_tm = vcpu->arch.tar;
|
||||
vcpu->arch.lr_tm = vcpu->arch.regs.link;
|
||||
vcpu->arch.cr_tm = vcpu->arch.cr;
|
||||
vcpu->arch.cr_tm = vcpu->arch.regs.ccr;
|
||||
vcpu->arch.xer_tm = vcpu->arch.regs.xer;
|
||||
vcpu->arch.vrsave_tm = vcpu->arch.vrsave;
|
||||
}
|
||||
@ -129,7 +129,7 @@ static inline void kvmppc_copyfrom_vcpu_tm(struct kvm_vcpu *vcpu)
|
||||
vcpu->arch.regs.ctr = vcpu->arch.ctr_tm;
|
||||
vcpu->arch.tar = vcpu->arch.tar_tm;
|
||||
vcpu->arch.regs.link = vcpu->arch.lr_tm;
|
||||
vcpu->arch.cr = vcpu->arch.cr_tm;
|
||||
vcpu->arch.regs.ccr = vcpu->arch.cr_tm;
|
||||
vcpu->arch.regs.xer = vcpu->arch.xer_tm;
|
||||
vcpu->arch.vrsave = vcpu->arch.vrsave_tm;
|
||||
}
|
||||
@ -141,7 +141,7 @@ static void kvmppc_emulate_treclaim(struct kvm_vcpu *vcpu, int ra_val)
|
||||
uint64_t texasr;
|
||||
|
||||
/* CR0 = 0 | MSR[TS] | 0 */
|
||||
vcpu->arch.cr = (vcpu->arch.cr & ~(CR0_MASK << CR0_SHIFT)) |
|
||||
vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)) |
|
||||
(((guest_msr & MSR_TS_MASK) >> (MSR_TS_S_LG - 1))
|
||||
<< CR0_SHIFT);
|
||||
|
||||
@ -220,7 +220,7 @@ void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val)
|
||||
tm_abort(ra_val);
|
||||
|
||||
/* CR0 = 0 | MSR[TS] | 0 */
|
||||
vcpu->arch.cr = (vcpu->arch.cr & ~(CR0_MASK << CR0_SHIFT)) |
|
||||
vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)) |
|
||||
(((guest_msr & MSR_TS_MASK) >> (MSR_TS_S_LG - 1))
|
||||
<< CR0_SHIFT);
|
||||
|
||||
@ -494,8 +494,8 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu,
|
||||
|
||||
if (!(kvmppc_get_msr(vcpu) & MSR_PR)) {
|
||||
preempt_disable();
|
||||
vcpu->arch.cr = (CR0_TBEGIN_FAILURE |
|
||||
(vcpu->arch.cr & ~(CR0_MASK << CR0_SHIFT)));
|
||||
vcpu->arch.regs.ccr = (CR0_TBEGIN_FAILURE |
|
||||
(vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)));
|
||||
|
||||
vcpu->arch.texasr = (TEXASR_FS | TEXASR_EXACT |
|
||||
(((u64)(TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
|
||||
|
||||
@ -410,8 +410,8 @@ static void kvmppc_dump_regs(struct kvm_vcpu *vcpu)
|
||||
vcpu->arch.shregs.sprg0, vcpu->arch.shregs.sprg1);
|
||||
pr_err("sprg2 = %.16llx sprg3 = %.16llx\n",
|
||||
vcpu->arch.shregs.sprg2, vcpu->arch.shregs.sprg3);
|
||||
pr_err("cr = %.8x xer = %.16lx dsisr = %.8x\n",
|
||||
vcpu->arch.cr, vcpu->arch.regs.xer, vcpu->arch.shregs.dsisr);
|
||||
pr_err("cr = %.8lx xer = %.16lx dsisr = %.8x\n",
|
||||
vcpu->arch.regs.ccr, vcpu->arch.regs.xer, vcpu->arch.shregs.dsisr);
|
||||
pr_err("dar = %.16llx\n", vcpu->arch.shregs.dar);
|
||||
pr_err("fault dar = %.16lx dsisr = %.8x\n",
|
||||
vcpu->arch.fault_dar, vcpu->arch.fault_dsisr);
|
||||
@ -3813,12 +3813,15 @@ static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu)
|
||||
/* Must be called with kvm->lock held and mmu_ready = 0 and no vcpus running */
|
||||
int kvmppc_switch_mmu_to_hpt(struct kvm *kvm)
|
||||
{
|
||||
kvmppc_rmap_reset(kvm);
|
||||
kvm->arch.process_table = 0;
|
||||
/* Mutual exclusion with kvm_unmap_hva_range etc. */
|
||||
spin_lock(&kvm->mmu_lock);
|
||||
kvm->arch.radix = 0;
|
||||
spin_unlock(&kvm->mmu_lock);
|
||||
kvmppc_free_radix(kvm);
|
||||
kvmppc_update_lpcr(kvm, LPCR_VPM1,
|
||||
LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR);
|
||||
kvmppc_rmap_reset(kvm);
|
||||
kvm->arch.radix = 0;
|
||||
kvm->arch.process_table = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -3831,10 +3834,14 @@ int kvmppc_switch_mmu_to_radix(struct kvm *kvm)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
kvmppc_rmap_reset(kvm);
|
||||
/* Mutual exclusion with kvm_unmap_hva_range etc. */
|
||||
spin_lock(&kvm->mmu_lock);
|
||||
kvm->arch.radix = 1;
|
||||
spin_unlock(&kvm->mmu_lock);
|
||||
kvmppc_free_hpt(&kvm->arch.hpt);
|
||||
kvmppc_update_lpcr(kvm, LPCR_UPRT | LPCR_GTSE | LPCR_HR,
|
||||
LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR);
|
||||
kvm->arch.radix = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -56,6 +56,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
|
||||
#define STACK_SLOT_DAWR (SFS-56)
|
||||
#define STACK_SLOT_DAWRX (SFS-64)
|
||||
#define STACK_SLOT_HFSCR (SFS-72)
|
||||
#define STACK_SLOT_AMR (SFS-80)
|
||||
#define STACK_SLOT_UAMOR (SFS-88)
|
||||
|
||||
/*
|
||||
* Call kvmppc_hv_entry in real mode.
|
||||
@ -760,11 +762,9 @@ BEGIN_FTR_SECTION
|
||||
mfspr r5, SPRN_TIDR
|
||||
mfspr r6, SPRN_PSSCR
|
||||
mfspr r7, SPRN_PID
|
||||
mfspr r8, SPRN_IAMR
|
||||
std r5, STACK_SLOT_TID(r1)
|
||||
std r6, STACK_SLOT_PSSCR(r1)
|
||||
std r7, STACK_SLOT_PID(r1)
|
||||
std r8, STACK_SLOT_IAMR(r1)
|
||||
mfspr r5, SPRN_HFSCR
|
||||
std r5, STACK_SLOT_HFSCR(r1)
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
|
||||
@ -772,11 +772,18 @@ BEGIN_FTR_SECTION
|
||||
mfspr r5, SPRN_CIABR
|
||||
mfspr r6, SPRN_DAWR
|
||||
mfspr r7, SPRN_DAWRX
|
||||
mfspr r8, SPRN_IAMR
|
||||
std r5, STACK_SLOT_CIABR(r1)
|
||||
std r6, STACK_SLOT_DAWR(r1)
|
||||
std r7, STACK_SLOT_DAWRX(r1)
|
||||
std r8, STACK_SLOT_IAMR(r1)
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
|
||||
|
||||
mfspr r5, SPRN_AMR
|
||||
std r5, STACK_SLOT_AMR(r1)
|
||||
mfspr r6, SPRN_UAMOR
|
||||
std r6, STACK_SLOT_UAMOR(r1)
|
||||
|
||||
BEGIN_FTR_SECTION
|
||||
/* Set partition DABR */
|
||||
/* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
|
||||
@ -1202,7 +1209,7 @@ BEGIN_FTR_SECTION
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
|
||||
|
||||
ld r5, VCPU_LR(r4)
|
||||
lwz r6, VCPU_CR(r4)
|
||||
ld r6, VCPU_CR(r4)
|
||||
mtlr r5
|
||||
mtcr r6
|
||||
|
||||
@ -1313,7 +1320,7 @@ kvmppc_interrupt_hv:
|
||||
std r3, VCPU_GPR(R12)(r9)
|
||||
/* CR is in the high half of r12 */
|
||||
srdi r4, r12, 32
|
||||
stw r4, VCPU_CR(r9)
|
||||
std r4, VCPU_CR(r9)
|
||||
BEGIN_FTR_SECTION
|
||||
ld r3, HSTATE_CFAR(r13)
|
||||
std r3, VCPU_CFAR(r9)
|
||||
@ -1713,22 +1720,25 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
|
||||
mtspr SPRN_PSPB, r0
|
||||
mtspr SPRN_WORT, r0
|
||||
BEGIN_FTR_SECTION
|
||||
mtspr SPRN_IAMR, r0
|
||||
mtspr SPRN_TCSCR, r0
|
||||
/* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
|
||||
li r0, 1
|
||||
sldi r0, r0, 31
|
||||
mtspr SPRN_MMCRS, r0
|
||||
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
|
||||
8:
|
||||
|
||||
/* Save and reset AMR and UAMOR before turning on the MMU */
|
||||
/* Save and restore AMR, IAMR and UAMOR before turning on the MMU */
|
||||
ld r8, STACK_SLOT_IAMR(r1)
|
||||
mtspr SPRN_IAMR, r8
|
||||
|
||||
8: /* Power7 jumps back in here */
|
||||
mfspr r5,SPRN_AMR
|
||||
mfspr r6,SPRN_UAMOR
|
||||
std r5,VCPU_AMR(r9)
|
||||
std r6,VCPU_UAMOR(r9)
|
||||
li r6,0
|
||||
mtspr SPRN_AMR,r6
|
||||
ld r5,STACK_SLOT_AMR(r1)
|
||||
ld r6,STACK_SLOT_UAMOR(r1)
|
||||
mtspr SPRN_AMR, r5
|
||||
mtspr SPRN_UAMOR, r6
|
||||
|
||||
/* Switch DSCR back to host value */
|
||||
@ -1897,11 +1907,9 @@ BEGIN_FTR_SECTION
|
||||
ld r5, STACK_SLOT_TID(r1)
|
||||
ld r6, STACK_SLOT_PSSCR(r1)
|
||||
ld r7, STACK_SLOT_PID(r1)
|
||||
ld r8, STACK_SLOT_IAMR(r1)
|
||||
mtspr SPRN_TIDR, r5
|
||||
mtspr SPRN_PSSCR, r6
|
||||
mtspr SPRN_PID, r7
|
||||
mtspr SPRN_IAMR, r8
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
|
||||
|
||||
#ifdef CONFIG_PPC_RADIX_MMU
|
||||
|
||||
@ -130,8 +130,8 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
|
||||
return RESUME_GUEST;
|
||||
}
|
||||
/* Set CR0 to indicate previous transactional state */
|
||||
vcpu->arch.cr = (vcpu->arch.cr & 0x0fffffff) |
|
||||
(((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 28);
|
||||
vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
|
||||
(((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
|
||||
/* L=1 => tresume, L=0 => tsuspend */
|
||||
if (instr & (1 << 21)) {
|
||||
if (MSR_TM_SUSPENDED(msr))
|
||||
@ -174,8 +174,8 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
|
||||
copy_from_checkpoint(vcpu);
|
||||
|
||||
/* Set CR0 to indicate previous transactional state */
|
||||
vcpu->arch.cr = (vcpu->arch.cr & 0x0fffffff) |
|
||||
(((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 28);
|
||||
vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
|
||||
(((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
|
||||
vcpu->arch.shregs.msr &= ~MSR_TS_MASK;
|
||||
return RESUME_GUEST;
|
||||
|
||||
@ -204,8 +204,8 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
|
||||
copy_to_checkpoint(vcpu);
|
||||
|
||||
/* Set CR0 to indicate previous transactional state */
|
||||
vcpu->arch.cr = (vcpu->arch.cr & 0x0fffffff) |
|
||||
(((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 28);
|
||||
vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
|
||||
(((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
|
||||
vcpu->arch.shregs.msr = msr | MSR_TS_S;
|
||||
return RESUME_GUEST;
|
||||
}
|
||||
|
||||
@ -89,7 +89,8 @@ int kvmhv_p9_tm_emulation_early(struct kvm_vcpu *vcpu)
|
||||
if (instr & (1 << 21))
|
||||
vcpu->arch.shregs.msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
|
||||
/* Set CR0 to 0b0010 */
|
||||
vcpu->arch.cr = (vcpu->arch.cr & 0x0fffffff) | 0x20000000;
|
||||
vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
|
||||
0x20000000;
|
||||
return 1;
|
||||
}
|
||||
|
||||
@ -105,5 +106,5 @@ void kvmhv_emulate_tm_rollback(struct kvm_vcpu *vcpu)
|
||||
vcpu->arch.shregs.msr &= ~MSR_TS_MASK; /* go to N state */
|
||||
vcpu->arch.regs.nip = vcpu->arch.tfhar;
|
||||
copy_from_checkpoint(vcpu);
|
||||
vcpu->arch.cr = (vcpu->arch.cr & 0x0fffffff) | 0xa0000000;
|
||||
vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | 0xa0000000;
|
||||
}
|
||||
|
||||
@ -167,7 +167,7 @@ void kvmppc_copy_to_svcpu(struct kvm_vcpu *vcpu)
|
||||
svcpu->gpr[11] = vcpu->arch.regs.gpr[11];
|
||||
svcpu->gpr[12] = vcpu->arch.regs.gpr[12];
|
||||
svcpu->gpr[13] = vcpu->arch.regs.gpr[13];
|
||||
svcpu->cr = vcpu->arch.cr;
|
||||
svcpu->cr = vcpu->arch.regs.ccr;
|
||||
svcpu->xer = vcpu->arch.regs.xer;
|
||||
svcpu->ctr = vcpu->arch.regs.ctr;
|
||||
svcpu->lr = vcpu->arch.regs.link;
|
||||
@ -249,7 +249,7 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu)
|
||||
vcpu->arch.regs.gpr[11] = svcpu->gpr[11];
|
||||
vcpu->arch.regs.gpr[12] = svcpu->gpr[12];
|
||||
vcpu->arch.regs.gpr[13] = svcpu->gpr[13];
|
||||
vcpu->arch.cr = svcpu->cr;
|
||||
vcpu->arch.regs.ccr = svcpu->cr;
|
||||
vcpu->arch.regs.xer = svcpu->xer;
|
||||
vcpu->arch.regs.ctr = svcpu->ctr;
|
||||
vcpu->arch.regs.link = svcpu->lr;
|
||||
|
||||
@ -186,7 +186,7 @@ END_BTB_FLUSH_SECTION
|
||||
*/
|
||||
PPC_LL r4, PACACURRENT(r13)
|
||||
PPC_LL r4, (THREAD + THREAD_KVM_VCPU)(r4)
|
||||
stw r10, VCPU_CR(r4)
|
||||
PPC_STL r10, VCPU_CR(r4)
|
||||
PPC_STL r11, VCPU_GPR(R4)(r4)
|
||||
PPC_STL r5, VCPU_GPR(R5)(r4)
|
||||
PPC_STL r6, VCPU_GPR(R6)(r4)
|
||||
@ -296,7 +296,7 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1)
|
||||
PPC_STL r4, VCPU_GPR(R4)(r11)
|
||||
PPC_LL r4, THREAD_NORMSAVE(0)(r10)
|
||||
PPC_STL r5, VCPU_GPR(R5)(r11)
|
||||
stw r13, VCPU_CR(r11)
|
||||
PPC_STL r13, VCPU_CR(r11)
|
||||
mfspr r5, \srr0
|
||||
PPC_STL r3, VCPU_GPR(R10)(r11)
|
||||
PPC_LL r3, THREAD_NORMSAVE(2)(r10)
|
||||
@ -323,7 +323,7 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1)
|
||||
PPC_STL r4, VCPU_GPR(R4)(r11)
|
||||
PPC_LL r4, GPR9(r8)
|
||||
PPC_STL r5, VCPU_GPR(R5)(r11)
|
||||
stw r9, VCPU_CR(r11)
|
||||
PPC_STL r9, VCPU_CR(r11)
|
||||
mfspr r5, \srr0
|
||||
PPC_STL r3, VCPU_GPR(R8)(r11)
|
||||
PPC_LL r3, GPR10(r8)
|
||||
@ -647,7 +647,7 @@ lightweight_exit:
|
||||
PPC_LL r3, VCPU_LR(r4)
|
||||
PPC_LL r5, VCPU_XER(r4)
|
||||
PPC_LL r6, VCPU_CTR(r4)
|
||||
lwz r7, VCPU_CR(r4)
|
||||
PPC_LL r7, VCPU_CR(r4)
|
||||
PPC_LL r8, VCPU_PC(r4)
|
||||
PPC_LD(r9, VCPU_SHARED_MSR, r11)
|
||||
PPC_LL r0, VCPU_GPR(R0)(r4)
|
||||
|
||||
@ -117,7 +117,6 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)
|
||||
|
||||
emulated = EMULATE_FAIL;
|
||||
vcpu->arch.regs.msr = vcpu->arch.shared->msr;
|
||||
vcpu->arch.regs.ccr = vcpu->arch.cr;
|
||||
if (analyse_instr(&op, &vcpu->arch.regs, inst) == 0) {
|
||||
int type = op.type & INSTR_TYPE_MASK;
|
||||
int size = GETSIZE(op.type);
|
||||
|
||||
@ -1859,11 +1859,20 @@ void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
|
||||
*
|
||||
* For guests on platforms before POWER9, we clamp the it limit to 1G
|
||||
* to avoid some funky things such as RTAS bugs etc...
|
||||
*
|
||||
* On POWER9 we limit to 1TB in case the host erroneously told us that
|
||||
* the RMA was >1TB. Effective address bits 0:23 are treated as zero
|
||||
* (meaning the access is aliased to zero i.e. addr = addr % 1TB)
|
||||
* for virtual real mode addressing and so it doesn't make sense to
|
||||
* have an area larger than 1TB as it can't be addressed.
|
||||
*/
|
||||
if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
|
||||
ppc64_rma_size = first_memblock_size;
|
||||
if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
|
||||
ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
|
||||
else
|
||||
ppc64_rma_size = min_t(u64, ppc64_rma_size,
|
||||
1UL << SID_SHIFT_1T);
|
||||
|
||||
/* Finally limit subsequent allocations */
|
||||
memblock_set_current_limit(ppc64_rma_size);
|
||||
|
||||
@ -414,3 +414,13 @@ bool arch_vma_access_permitted(struct vm_area_struct *vma, bool write,
|
||||
|
||||
return pkey_access_permitted(vma_pkey(vma), write, execute);
|
||||
}
|
||||
|
||||
void arch_dup_pkeys(struct mm_struct *oldmm, struct mm_struct *mm)
|
||||
{
|
||||
if (static_branch_likely(&pkey_disabled))
|
||||
return;
|
||||
|
||||
/* Duplicate the oldmm pkey state in mm: */
|
||||
mm_pkey_allocation_map(mm) = mm_pkey_allocation_map(oldmm);
|
||||
mm->context.execute_only_pkey = oldmm->context.execute_only_pkey;
|
||||
}
|
||||
|
||||
@ -132,7 +132,6 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
|
||||
{
|
||||
unsigned long return_hooker = (unsigned long)&return_to_handler;
|
||||
unsigned long old;
|
||||
int err;
|
||||
|
||||
if (unlikely(atomic_read(¤t->tracing_graph_pause)))
|
||||
return;
|
||||
|
||||
@ -117,7 +117,7 @@ static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
|
||||
}
|
||||
|
||||
#define KVM_PERMILLE_MMU_PAGES 20
|
||||
#define KVM_MIN_ALLOC_MMU_PAGES 64
|
||||
#define KVM_MIN_ALLOC_MMU_PAGES 64UL
|
||||
#define KVM_MMU_HASH_SHIFT 12
|
||||
#define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
|
||||
#define KVM_MIN_FREE_MMU_PAGES 5
|
||||
@ -784,6 +784,9 @@ struct kvm_hv {
|
||||
u64 hv_reenlightenment_control;
|
||||
u64 hv_tsc_emulation_control;
|
||||
u64 hv_tsc_emulation_status;
|
||||
|
||||
/* How many vCPUs have VP index != vCPU index */
|
||||
atomic_t num_mismatched_vp_indexes;
|
||||
};
|
||||
|
||||
enum kvm_irqchip_mode {
|
||||
@ -793,9 +796,9 @@ enum kvm_irqchip_mode {
|
||||
};
|
||||
|
||||
struct kvm_arch {
|
||||
unsigned int n_used_mmu_pages;
|
||||
unsigned int n_requested_mmu_pages;
|
||||
unsigned int n_max_mmu_pages;
|
||||
unsigned long n_used_mmu_pages;
|
||||
unsigned long n_requested_mmu_pages;
|
||||
unsigned long n_max_mmu_pages;
|
||||
unsigned int indirect_shadow_pages;
|
||||
unsigned long mmu_valid_gen;
|
||||
struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
|
||||
@ -1198,8 +1201,8 @@ void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
|
||||
gfn_t gfn_offset, unsigned long mask);
|
||||
void kvm_mmu_zap_all(struct kvm *kvm);
|
||||
void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen);
|
||||
unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
|
||||
void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
|
||||
unsigned long kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
|
||||
void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages);
|
||||
|
||||
int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3);
|
||||
bool pdptrs_changed(struct kvm_vcpu *vcpu);
|
||||
|
||||
@ -53,7 +53,7 @@ int ftrace_arch_code_modify_post_process(void)
|
||||
union ftrace_code_union {
|
||||
char code[MCOUNT_INSN_SIZE];
|
||||
struct {
|
||||
unsigned char e8;
|
||||
unsigned char op;
|
||||
int offset;
|
||||
} __attribute__((packed));
|
||||
};
|
||||
@ -63,20 +63,23 @@ static int ftrace_calc_offset(long ip, long addr)
|
||||
return (int)(addr - ip);
|
||||
}
|
||||
|
||||
static unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
|
||||
static unsigned char *
|
||||
ftrace_text_replace(unsigned char op, unsigned long ip, unsigned long addr)
|
||||
{
|
||||
static union ftrace_code_union calc;
|
||||
|
||||
calc.e8 = 0xe8;
|
||||
calc.op = op;
|
||||
calc.offset = ftrace_calc_offset(ip + MCOUNT_INSN_SIZE, addr);
|
||||
|
||||
/*
|
||||
* No locking needed, this must be called via kstop_machine
|
||||
* which in essence is like running on a uniprocessor machine.
|
||||
*/
|
||||
return calc.code;
|
||||
}
|
||||
|
||||
static unsigned char *
|
||||
ftrace_call_replace(unsigned long ip, unsigned long addr)
|
||||
{
|
||||
return ftrace_text_replace(0xe8, ip, addr);
|
||||
}
|
||||
|
||||
static inline int
|
||||
within(unsigned long addr, unsigned long start, unsigned long end)
|
||||
{
|
||||
@ -686,22 +689,6 @@ int __init ftrace_dyn_arch_init(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_X86_64) || defined(CONFIG_FUNCTION_GRAPH_TRACER)
|
||||
static unsigned char *ftrace_jmp_replace(unsigned long ip, unsigned long addr)
|
||||
{
|
||||
static union ftrace_code_union calc;
|
||||
|
||||
/* Jmp not a call (ignore the .e8) */
|
||||
calc.e8 = 0xe9;
|
||||
calc.offset = ftrace_calc_offset(ip + MCOUNT_INSN_SIZE, addr);
|
||||
|
||||
/*
|
||||
* ftrace external locks synchronize the access to the static variable.
|
||||
*/
|
||||
return calc.code;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Currently only x86_64 supports dynamic trampolines */
|
||||
#ifdef CONFIG_X86_64
|
||||
|
||||
@ -923,8 +910,8 @@ static void *addr_from_call(void *ptr)
|
||||
return NULL;
|
||||
|
||||
/* Make sure this is a call */
|
||||
if (WARN_ON_ONCE(calc.e8 != 0xe8)) {
|
||||
pr_warn("Expected e8, got %x\n", calc.e8);
|
||||
if (WARN_ON_ONCE(calc.op != 0xe8)) {
|
||||
pr_warn("Expected e8, got %x\n", calc.op);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@ -995,6 +982,11 @@ void arch_ftrace_trampoline_free(struct ftrace_ops *ops)
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
extern void ftrace_graph_call(void);
|
||||
|
||||
static unsigned char *ftrace_jmp_replace(unsigned long ip, unsigned long addr)
|
||||
{
|
||||
return ftrace_text_replace(0xe9, ip, addr);
|
||||
}
|
||||
|
||||
static int ftrace_mod_jmp(unsigned long ip, void *func)
|
||||
{
|
||||
unsigned char *new;
|
||||
|
||||
@ -117,12 +117,8 @@ static u64 kvm_sched_clock_read(void)
|
||||
|
||||
static inline void kvm_sched_clock_init(bool stable)
|
||||
{
|
||||
if (!stable) {
|
||||
pv_time_ops.sched_clock = kvm_clock_read;
|
||||
if (!stable)
|
||||
clear_sched_clock_stable();
|
||||
return;
|
||||
}
|
||||
|
||||
kvm_sched_clock_offset = kvm_clock_read();
|
||||
pv_time_ops.sched_clock = kvm_sched_clock_read;
|
||||
|
||||
|
||||
@ -1251,7 +1251,7 @@ void __init setup_arch(char **cmdline_p)
|
||||
x86_init.hyper.guest_late_init();
|
||||
|
||||
e820__reserve_resources();
|
||||
e820__register_nosave_regions(max_low_pfn);
|
||||
e820__register_nosave_regions(max_pfn);
|
||||
|
||||
x86_init.resources.reserve_resources();
|
||||
|
||||
|
||||
@ -2331,12 +2331,16 @@ static int em_lseg(struct x86_emulate_ctxt *ctxt)
|
||||
|
||||
static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
|
||||
{
|
||||
#ifdef CONFIG_X86_64
|
||||
u32 eax, ebx, ecx, edx;
|
||||
|
||||
eax = 0x80000001;
|
||||
ecx = 0;
|
||||
ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
|
||||
return edx & bit(X86_FEATURE_LM);
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
#define GET_SMSTATE(type, smbase, offset) \
|
||||
@ -2381,6 +2385,7 @@ static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
|
||||
return X86EMUL_CONTINUE;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
|
||||
{
|
||||
struct desc_struct desc;
|
||||
@ -2399,6 +2404,7 @@ static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
|
||||
ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
|
||||
return X86EMUL_CONTINUE;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
|
||||
u64 cr0, u64 cr3, u64 cr4)
|
||||
@ -2499,6 +2505,7 @@ static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase)
|
||||
return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
|
||||
{
|
||||
struct desc_struct desc;
|
||||
@ -2560,6 +2567,7 @@ static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
|
||||
|
||||
return X86EMUL_CONTINUE;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int em_rsm(struct x86_emulate_ctxt *ctxt)
|
||||
{
|
||||
@ -2616,9 +2624,11 @@ static int em_rsm(struct x86_emulate_ctxt *ctxt)
|
||||
if (ctxt->ops->pre_leave_smm(ctxt, smbase))
|
||||
return X86EMUL_UNHANDLEABLE;
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
if (emulator_has_longmode(ctxt))
|
||||
ret = rsm_load_state_64(ctxt, smbase + 0x8000);
|
||||
else
|
||||
#endif
|
||||
ret = rsm_load_state_32(ctxt, smbase + 0x8000);
|
||||
|
||||
if (ret != X86EMUL_CONTINUE) {
|
||||
|
||||
@ -132,8 +132,10 @@ static struct kvm_vcpu *get_vcpu_by_vpidx(struct kvm *kvm, u32 vpidx)
|
||||
struct kvm_vcpu *vcpu = NULL;
|
||||
int i;
|
||||
|
||||
if (vpidx < KVM_MAX_VCPUS)
|
||||
vcpu = kvm_get_vcpu(kvm, vpidx);
|
||||
if (vpidx >= KVM_MAX_VCPUS)
|
||||
return NULL;
|
||||
|
||||
vcpu = kvm_get_vcpu(kvm, vpidx);
|
||||
if (vcpu && vcpu_to_hv_vcpu(vcpu)->vp_index == vpidx)
|
||||
return vcpu;
|
||||
kvm_for_each_vcpu(i, vcpu, kvm)
|
||||
@ -689,6 +691,24 @@ void kvm_hv_vcpu_uninit(struct kvm_vcpu *vcpu)
|
||||
stimer_cleanup(&hv_vcpu->stimer[i]);
|
||||
}
|
||||
|
||||
bool kvm_hv_assist_page_enabled(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
if (!(vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE))
|
||||
return false;
|
||||
return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_hv_assist_page_enabled);
|
||||
|
||||
bool kvm_hv_get_assist_page(struct kvm_vcpu *vcpu,
|
||||
struct hv_vp_assist_page *assist_page)
|
||||
{
|
||||
if (!kvm_hv_assist_page_enabled(vcpu))
|
||||
return false;
|
||||
return !kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data,
|
||||
assist_page, sizeof(*assist_page));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_hv_get_assist_page);
|
||||
|
||||
static void stimer_prepare_msg(struct kvm_vcpu_hv_stimer *stimer)
|
||||
{
|
||||
struct hv_message *msg = &stimer->msg;
|
||||
@ -1040,21 +1060,41 @@ static u64 current_task_runtime_100ns(void)
|
||||
|
||||
static int kvm_hv_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data, bool host)
|
||||
{
|
||||
struct kvm_vcpu_hv *hv = &vcpu->arch.hyperv;
|
||||
struct kvm_vcpu_hv *hv_vcpu = &vcpu->arch.hyperv;
|
||||
|
||||
switch (msr) {
|
||||
case HV_X64_MSR_VP_INDEX:
|
||||
if (!host)
|
||||
case HV_X64_MSR_VP_INDEX: {
|
||||
struct kvm_hv *hv = &vcpu->kvm->arch.hyperv;
|
||||
int vcpu_idx = kvm_vcpu_get_idx(vcpu);
|
||||
u32 new_vp_index = (u32)data;
|
||||
|
||||
if (!host || new_vp_index >= KVM_MAX_VCPUS)
|
||||
return 1;
|
||||
hv->vp_index = (u32)data;
|
||||
|
||||
if (new_vp_index == hv_vcpu->vp_index)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* The VP index is initialized to vcpu_index by
|
||||
* kvm_hv_vcpu_postcreate so they initially match. Now the
|
||||
* VP index is changing, adjust num_mismatched_vp_indexes if
|
||||
* it now matches or no longer matches vcpu_idx.
|
||||
*/
|
||||
if (hv_vcpu->vp_index == vcpu_idx)
|
||||
atomic_inc(&hv->num_mismatched_vp_indexes);
|
||||
else if (new_vp_index == vcpu_idx)
|
||||
atomic_dec(&hv->num_mismatched_vp_indexes);
|
||||
|
||||
hv_vcpu->vp_index = new_vp_index;
|
||||
break;
|
||||
}
|
||||
case HV_X64_MSR_VP_ASSIST_PAGE: {
|
||||
u64 gfn;
|
||||
unsigned long addr;
|
||||
|
||||
if (!(data & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE)) {
|
||||
hv->hv_vapic = data;
|
||||
if (kvm_lapic_enable_pv_eoi(vcpu, 0))
|
||||
hv_vcpu->hv_vapic = data;
|
||||
if (kvm_lapic_enable_pv_eoi(vcpu, 0, 0))
|
||||
return 1;
|
||||
break;
|
||||
}
|
||||
@ -1064,10 +1104,11 @@ static int kvm_hv_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data, bool host)
|
||||
return 1;
|
||||
if (__clear_user((void __user *)addr, PAGE_SIZE))
|
||||
return 1;
|
||||
hv->hv_vapic = data;
|
||||
hv_vcpu->hv_vapic = data;
|
||||
kvm_vcpu_mark_page_dirty(vcpu, gfn);
|
||||
if (kvm_lapic_enable_pv_eoi(vcpu,
|
||||
gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
|
||||
gfn_to_gpa(gfn) | KVM_MSR_ENABLED,
|
||||
sizeof(struct hv_vp_assist_page)))
|
||||
return 1;
|
||||
break;
|
||||
}
|
||||
@ -1080,7 +1121,7 @@ static int kvm_hv_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data, bool host)
|
||||
case HV_X64_MSR_VP_RUNTIME:
|
||||
if (!host)
|
||||
return 1;
|
||||
hv->runtime_offset = data - current_task_runtime_100ns();
|
||||
hv_vcpu->runtime_offset = data - current_task_runtime_100ns();
|
||||
break;
|
||||
case HV_X64_MSR_SCONTROL:
|
||||
case HV_X64_MSR_SVERSION:
|
||||
@ -1172,11 +1213,11 @@ static int kvm_hv_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata,
|
||||
bool host)
|
||||
{
|
||||
u64 data = 0;
|
||||
struct kvm_vcpu_hv *hv = &vcpu->arch.hyperv;
|
||||
struct kvm_vcpu_hv *hv_vcpu = &vcpu->arch.hyperv;
|
||||
|
||||
switch (msr) {
|
||||
case HV_X64_MSR_VP_INDEX:
|
||||
data = hv->vp_index;
|
||||
data = hv_vcpu->vp_index;
|
||||
break;
|
||||
case HV_X64_MSR_EOI:
|
||||
return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
|
||||
@ -1185,10 +1226,10 @@ static int kvm_hv_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata,
|
||||
case HV_X64_MSR_TPR:
|
||||
return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
|
||||
case HV_X64_MSR_VP_ASSIST_PAGE:
|
||||
data = hv->hv_vapic;
|
||||
data = hv_vcpu->hv_vapic;
|
||||
break;
|
||||
case HV_X64_MSR_VP_RUNTIME:
|
||||
data = current_task_runtime_100ns() + hv->runtime_offset;
|
||||
data = current_task_runtime_100ns() + hv_vcpu->runtime_offset;
|
||||
break;
|
||||
case HV_X64_MSR_SCONTROL:
|
||||
case HV_X64_MSR_SVERSION:
|
||||
|
||||
@ -62,6 +62,10 @@ void kvm_hv_vcpu_init(struct kvm_vcpu *vcpu);
|
||||
void kvm_hv_vcpu_postcreate(struct kvm_vcpu *vcpu);
|
||||
void kvm_hv_vcpu_uninit(struct kvm_vcpu *vcpu);
|
||||
|
||||
bool kvm_hv_assist_page_enabled(struct kvm_vcpu *vcpu);
|
||||
bool kvm_hv_get_assist_page(struct kvm_vcpu *vcpu,
|
||||
struct hv_vp_assist_page *assist_page);
|
||||
|
||||
static inline struct kvm_vcpu_hv_stimer *vcpu_to_stimer(struct kvm_vcpu *vcpu,
|
||||
int timer_index)
|
||||
{
|
||||
|
||||
@ -172,3 +172,10 @@ void __kvm_migrate_timers(struct kvm_vcpu *vcpu)
|
||||
__kvm_migrate_apic_timer(vcpu);
|
||||
__kvm_migrate_pit_timer(vcpu);
|
||||
}
|
||||
|
||||
bool kvm_arch_irqfd_allowed(struct kvm *kvm, struct kvm_irqfd *args)
|
||||
{
|
||||
bool resample = args->flags & KVM_IRQFD_FLAG_RESAMPLE;
|
||||
|
||||
return resample ? irqchip_kernel(kvm) : irqchip_in_kernel(kvm);
|
||||
}
|
||||
|
||||
@ -114,6 +114,7 @@ static inline int irqchip_in_kernel(struct kvm *kvm)
|
||||
return mode != KVM_IRQCHIP_NONE;
|
||||
}
|
||||
|
||||
bool kvm_arch_irqfd_allowed(struct kvm *kvm, struct kvm_irqfd *args);
|
||||
void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu);
|
||||
void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu);
|
||||
void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu);
|
||||
|
||||
@ -2633,17 +2633,25 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
|
||||
int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
|
||||
{
|
||||
u64 addr = data & ~KVM_MSR_ENABLED;
|
||||
struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
|
||||
unsigned long new_len;
|
||||
|
||||
if (!IS_ALIGNED(addr, 4))
|
||||
return 1;
|
||||
|
||||
vcpu->arch.pv_eoi.msr_val = data;
|
||||
if (!pv_eoi_enabled(vcpu))
|
||||
return 0;
|
||||
return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
|
||||
addr, sizeof(u8));
|
||||
|
||||
if (addr == ghc->gpa && len <= ghc->len)
|
||||
new_len = ghc->len;
|
||||
else
|
||||
new_len = len;
|
||||
|
||||
return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
|
||||
}
|
||||
|
||||
void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
|
||||
|
||||
@ -120,7 +120,7 @@ static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
|
||||
return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
|
||||
}
|
||||
|
||||
int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
|
||||
int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
|
||||
void kvm_lapic_init(void);
|
||||
void kvm_lapic_exit(void);
|
||||
|
||||
|
||||
@ -1954,7 +1954,7 @@ static int is_empty_shadow_page(u64 *spt)
|
||||
* aggregate version in order to make the slab shrinker
|
||||
* faster
|
||||
*/
|
||||
static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
|
||||
static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
|
||||
{
|
||||
kvm->arch.n_used_mmu_pages += nr;
|
||||
percpu_counter_add(&kvm_total_used_mmu_pages, nr);
|
||||
@ -2704,7 +2704,7 @@ static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
|
||||
* Changing the number of mmu pages allocated to the vm
|
||||
* Note: if goal_nr_mmu_pages is too small, you will get dead lock
|
||||
*/
|
||||
void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
|
||||
void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
|
||||
{
|
||||
LIST_HEAD(invalid_list);
|
||||
|
||||
@ -5926,10 +5926,10 @@ out:
|
||||
/*
|
||||
* Caculate mmu pages needed for kvm.
|
||||
*/
|
||||
unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
|
||||
unsigned long kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
|
||||
{
|
||||
unsigned int nr_mmu_pages;
|
||||
unsigned int nr_pages = 0;
|
||||
unsigned long nr_mmu_pages;
|
||||
unsigned long nr_pages = 0;
|
||||
struct kvm_memslots *slots;
|
||||
struct kvm_memory_slot *memslot;
|
||||
int i;
|
||||
@ -5942,8 +5942,7 @@ unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
|
||||
}
|
||||
|
||||
nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
|
||||
nr_mmu_pages = max(nr_mmu_pages,
|
||||
(unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
|
||||
nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
|
||||
|
||||
return nr_mmu_pages;
|
||||
}
|
||||
|
||||
@ -69,7 +69,7 @@ bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
|
||||
int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
|
||||
u64 fault_address, char *insn, int insn_len);
|
||||
|
||||
static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
|
||||
static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
|
||||
{
|
||||
if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
|
||||
return kvm->arch.n_max_mmu_pages -
|
||||
|
||||
@ -48,11 +48,6 @@ static bool msr_mtrr_valid(unsigned msr)
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool valid_pat_type(unsigned t)
|
||||
{
|
||||
return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
|
||||
}
|
||||
|
||||
static bool valid_mtrr_type(unsigned t)
|
||||
{
|
||||
return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
|
||||
@ -67,10 +62,7 @@ bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
|
||||
return false;
|
||||
|
||||
if (msr == MSR_IA32_CR_PAT) {
|
||||
for (i = 0; i < 8; i++)
|
||||
if (!valid_pat_type((data >> (i * 8)) & 0xff))
|
||||
return false;
|
||||
return true;
|
||||
return kvm_pat_valid(data);
|
||||
} else if (msr == MSR_MTRRdefType) {
|
||||
if (data & ~0xcff)
|
||||
return false;
|
||||
|
||||
@ -5622,6 +5622,7 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
|
||||
svm->vmcb->save.cr2 = vcpu->arch.cr2;
|
||||
|
||||
clgi();
|
||||
kvm_load_guest_xcr0(vcpu);
|
||||
|
||||
/*
|
||||
* If this vCPU has touched SPEC_CTRL, restore the guest's value if
|
||||
@ -5769,6 +5770,7 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
|
||||
if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
|
||||
kvm_before_interrupt(&svm->vcpu);
|
||||
|
||||
kvm_put_guest_xcr0(vcpu);
|
||||
stgi();
|
||||
|
||||
/* Any pending NMI will happen here */
|
||||
|
||||
@ -4135,7 +4135,10 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
||||
return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
|
||||
&msr_info->data);
|
||||
case MSR_IA32_XSS:
|
||||
if (!vmx_xsaves_supported())
|
||||
if (!vmx_xsaves_supported() ||
|
||||
(!msr_info->host_initiated &&
|
||||
!(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
|
||||
guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
|
||||
return 1;
|
||||
msr_info->data = vcpu->arch.ia32_xss;
|
||||
break;
|
||||
@ -4265,9 +4268,10 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
||||
MSR_TYPE_W);
|
||||
break;
|
||||
case MSR_IA32_CR_PAT:
|
||||
if (!kvm_pat_valid(data))
|
||||
return 1;
|
||||
|
||||
if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
|
||||
if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
|
||||
return 1;
|
||||
vmcs_write64(GUEST_IA32_PAT, data);
|
||||
vcpu->arch.pat = data;
|
||||
break;
|
||||
@ -4301,7 +4305,10 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
||||
return 1;
|
||||
return vmx_set_vmx_msr(vcpu, msr_index, data);
|
||||
case MSR_IA32_XSS:
|
||||
if (!vmx_xsaves_supported())
|
||||
if (!vmx_xsaves_supported() ||
|
||||
(!msr_info->host_initiated &&
|
||||
!(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
|
||||
guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
|
||||
return 1;
|
||||
/*
|
||||
* The only supported bit as of Skylake is bit 8, but
|
||||
@ -10437,28 +10444,21 @@ static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
|
||||
|
||||
static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
|
||||
{
|
||||
u32 exit_intr_info = 0;
|
||||
u16 basic_exit_reason = (u16)vmx->exit_reason;
|
||||
|
||||
if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
|
||||
|| basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
|
||||
if (vmx->exit_reason != EXIT_REASON_EXCEPTION_NMI)
|
||||
return;
|
||||
|
||||
if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
|
||||
exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
|
||||
vmx->exit_intr_info = exit_intr_info;
|
||||
vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
|
||||
|
||||
/* if exit due to PF check for async PF */
|
||||
if (is_page_fault(exit_intr_info))
|
||||
if (is_page_fault(vmx->exit_intr_info))
|
||||
vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
|
||||
|
||||
/* Handle machine checks before interrupts are enabled */
|
||||
if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
|
||||
is_machine_check(exit_intr_info))
|
||||
if (is_machine_check(vmx->exit_intr_info))
|
||||
kvm_machine_check();
|
||||
|
||||
/* We need to handle NMIs before interrupts are enabled */
|
||||
if (is_nmi(exit_intr_info)) {
|
||||
if (is_nmi(vmx->exit_intr_info)) {
|
||||
kvm_before_interrupt(&vmx->vcpu);
|
||||
asm("int $2");
|
||||
kvm_after_interrupt(&vmx->vcpu);
|
||||
@ -10756,6 +10756,8 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
|
||||
if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
|
||||
vmx_set_interrupt_shadow(vcpu, 0);
|
||||
|
||||
kvm_load_guest_xcr0(vcpu);
|
||||
|
||||
if (static_cpu_has(X86_FEATURE_PKU) &&
|
||||
kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
|
||||
vcpu->arch.pkru != vmx->host_pkru)
|
||||
@ -10808,7 +10810,7 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
|
||||
"mov %%" _ASM_AX", %%cr2 \n\t"
|
||||
"3: \n\t"
|
||||
/* Check if vmlaunch of vmresume is needed */
|
||||
"cmpl $0, %c[launched](%0) \n\t"
|
||||
"cmpb $0, %c[launched](%0) \n\t"
|
||||
/* Load guest registers. Don't clobber flags. */
|
||||
"mov %c[rax](%0), %%" _ASM_AX " \n\t"
|
||||
"mov %c[rbx](%0), %%" _ASM_BX " \n\t"
|
||||
@ -10971,10 +10973,15 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
|
||||
__write_pkru(vmx->host_pkru);
|
||||
}
|
||||
|
||||
kvm_put_guest_xcr0(vcpu);
|
||||
|
||||
vmx->nested.nested_run_pending = 0;
|
||||
vmx->idt_vectoring_info = 0;
|
||||
|
||||
vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
|
||||
if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
|
||||
kvm_machine_check();
|
||||
|
||||
if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
|
||||
return;
|
||||
|
||||
|
||||
@ -713,7 +713,7 @@ void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_lmsw);
|
||||
|
||||
static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
|
||||
void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
|
||||
!vcpu->guest_xcr0_loaded) {
|
||||
@ -723,8 +723,9 @@ static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
|
||||
vcpu->guest_xcr0_loaded = 1;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
|
||||
|
||||
static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
|
||||
void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
if (vcpu->guest_xcr0_loaded) {
|
||||
if (vcpu->arch.xcr0 != host_xcr0)
|
||||
@ -732,6 +733,7 @@ static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
|
||||
vcpu->guest_xcr0_loaded = 0;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
|
||||
|
||||
static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
|
||||
{
|
||||
@ -2494,7 +2496,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
||||
|
||||
break;
|
||||
case MSR_KVM_PV_EOI_EN:
|
||||
if (kvm_lapic_enable_pv_eoi(vcpu, data))
|
||||
if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
|
||||
return 1;
|
||||
break;
|
||||
|
||||
@ -4116,7 +4118,7 @@ static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
|
||||
}
|
||||
|
||||
static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
|
||||
u32 kvm_nr_mmu_pages)
|
||||
unsigned long kvm_nr_mmu_pages)
|
||||
{
|
||||
if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
|
||||
return -EINVAL;
|
||||
@ -4130,7 +4132,7 @@ static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
|
||||
static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
|
||||
{
|
||||
return kvm->arch.n_max_mmu_pages;
|
||||
}
|
||||
@ -7225,9 +7227,9 @@ static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
|
||||
put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
|
||||
{
|
||||
#ifdef CONFIG_X86_64
|
||||
struct desc_ptr dt;
|
||||
struct kvm_segment seg;
|
||||
unsigned long val;
|
||||
@ -7277,10 +7279,8 @@ static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
|
||||
|
||||
for (i = 0; i < 6; i++)
|
||||
enter_smm_save_seg_64(vcpu, buf, i);
|
||||
#else
|
||||
WARN_ON_ONCE(1);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
static void enter_smm(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
@ -7291,9 +7291,11 @@ static void enter_smm(struct kvm_vcpu *vcpu)
|
||||
|
||||
trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
|
||||
memset(buf, 0, 512);
|
||||
#ifdef CONFIG_X86_64
|
||||
if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
|
||||
enter_smm_save_state_64(vcpu, buf);
|
||||
else
|
||||
#endif
|
||||
enter_smm_save_state_32(vcpu, buf);
|
||||
|
||||
/*
|
||||
@ -7351,8 +7353,10 @@ static void enter_smm(struct kvm_vcpu *vcpu)
|
||||
kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
|
||||
kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
|
||||
kvm_x86_ops->set_efer(vcpu, 0);
|
||||
#endif
|
||||
|
||||
kvm_update_cpuid(vcpu);
|
||||
kvm_mmu_reset_context(vcpu);
|
||||
@ -7649,8 +7653,6 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
|
||||
goto cancel_injection;
|
||||
}
|
||||
|
||||
kvm_load_guest_xcr0(vcpu);
|
||||
|
||||
if (req_immediate_exit) {
|
||||
kvm_make_request(KVM_REQ_EVENT, vcpu);
|
||||
kvm_x86_ops->request_immediate_exit(vcpu);
|
||||
@ -7703,8 +7705,6 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
|
||||
vcpu->mode = OUTSIDE_GUEST_MODE;
|
||||
smp_wmb();
|
||||
|
||||
kvm_put_guest_xcr0(vcpu);
|
||||
|
||||
kvm_before_interrupt(vcpu);
|
||||
kvm_x86_ops->handle_external_intr(vcpu);
|
||||
kvm_after_interrupt(vcpu);
|
||||
|
||||
@ -345,4 +345,16 @@ static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
|
||||
__this_cpu_write(current_vcpu, NULL);
|
||||
}
|
||||
|
||||
|
||||
static inline bool kvm_pat_valid(u64 data)
|
||||
{
|
||||
if (data & 0xF8F8F8F8F8F8F8F8ull)
|
||||
return false;
|
||||
/* 0, 1, 4, 5, 6, 7 are valid values. */
|
||||
return (data | ((data & 0x0202020202020202ull) << 1)) == data;
|
||||
}
|
||||
|
||||
void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu);
|
||||
void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu);
|
||||
|
||||
#endif
|
||||
|
||||
@ -816,7 +816,8 @@ void blk_cleanup_queue(struct request_queue *q)
|
||||
blk_exit_queue(q);
|
||||
|
||||
if (q->mq_ops)
|
||||
blk_mq_free_queue(q);
|
||||
blk_mq_exit_queue(q);
|
||||
|
||||
percpu_ref_exit(&q->q_usage_counter);
|
||||
|
||||
spin_lock_irq(lock);
|
||||
|
||||
@ -562,15 +562,12 @@ static void blkcg_iolatency_done_bio(struct rq_qos *rqos, struct bio *bio)
|
||||
u64 now = ktime_to_ns(ktime_get());
|
||||
bool issue_as_root = bio_issue_as_root_blkg(bio);
|
||||
bool enabled = false;
|
||||
int inflight = 0;
|
||||
|
||||
blkg = bio->bi_blkg;
|
||||
if (!blkg)
|
||||
return;
|
||||
|
||||
/* We didn't actually submit this bio, don't account it. */
|
||||
if (bio->bi_status == BLK_STS_AGAIN)
|
||||
return;
|
||||
|
||||
iolat = blkg_to_lat(bio->bi_blkg);
|
||||
if (!iolat)
|
||||
return;
|
||||
@ -587,45 +584,28 @@ static void blkcg_iolatency_done_bio(struct rq_qos *rqos, struct bio *bio)
|
||||
}
|
||||
rqw = &iolat->rq_wait;
|
||||
|
||||
atomic_dec(&rqw->inflight);
|
||||
if (iolat->min_lat_nsec == 0)
|
||||
goto next;
|
||||
iolatency_record_time(iolat, &bio->bi_issue, now,
|
||||
issue_as_root);
|
||||
window_start = atomic64_read(&iolat->window_start);
|
||||
if (now > window_start &&
|
||||
(now - window_start) >= iolat->cur_win_nsec) {
|
||||
if (atomic64_cmpxchg(&iolat->window_start,
|
||||
window_start, now) == window_start)
|
||||
iolatency_check_latencies(iolat, now);
|
||||
inflight = atomic_dec_return(&rqw->inflight);
|
||||
WARN_ON_ONCE(inflight < 0);
|
||||
/*
|
||||
* If bi_status is BLK_STS_AGAIN, the bio wasn't actually
|
||||
* submitted, so do not account for it.
|
||||
*/
|
||||
if (iolat->min_lat_nsec && bio->bi_status != BLK_STS_AGAIN) {
|
||||
iolatency_record_time(iolat, &bio->bi_issue, now,
|
||||
issue_as_root);
|
||||
window_start = atomic64_read(&iolat->window_start);
|
||||
if (now > window_start &&
|
||||
(now - window_start) >= iolat->cur_win_nsec) {
|
||||
if (atomic64_cmpxchg(&iolat->window_start,
|
||||
window_start, now) == window_start)
|
||||
iolatency_check_latencies(iolat, now);
|
||||
}
|
||||
}
|
||||
next:
|
||||
wake_up(&rqw->wait);
|
||||
blkg = blkg->parent;
|
||||
}
|
||||
}
|
||||
|
||||
static void blkcg_iolatency_cleanup(struct rq_qos *rqos, struct bio *bio)
|
||||
{
|
||||
struct blkcg_gq *blkg;
|
||||
|
||||
blkg = bio->bi_blkg;
|
||||
while (blkg && blkg->parent) {
|
||||
struct rq_wait *rqw;
|
||||
struct iolatency_grp *iolat;
|
||||
|
||||
iolat = blkg_to_lat(blkg);
|
||||
if (!iolat)
|
||||
goto next;
|
||||
|
||||
rqw = &iolat->rq_wait;
|
||||
atomic_dec(&rqw->inflight);
|
||||
wake_up(&rqw->wait);
|
||||
next:
|
||||
blkg = blkg->parent;
|
||||
}
|
||||
}
|
||||
|
||||
static void blkcg_iolatency_exit(struct rq_qos *rqos)
|
||||
{
|
||||
struct blk_iolatency *blkiolat = BLKIOLATENCY(rqos);
|
||||
@ -637,7 +617,6 @@ static void blkcg_iolatency_exit(struct rq_qos *rqos)
|
||||
|
||||
static struct rq_qos_ops blkcg_iolatency_ops = {
|
||||
.throttle = blkcg_iolatency_throttle,
|
||||
.cleanup = blkcg_iolatency_cleanup,
|
||||
.done_bio = blkcg_iolatency_done_bio,
|
||||
.exit = blkcg_iolatency_exit,
|
||||
};
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <linux/blk-mq.h>
|
||||
#include "blk.h"
|
||||
#include "blk-mq.h"
|
||||
#include "blk-mq-tag.h"
|
||||
|
||||
@ -21,6 +22,11 @@ static void blk_mq_hw_sysfs_release(struct kobject *kobj)
|
||||
{
|
||||
struct blk_mq_hw_ctx *hctx = container_of(kobj, struct blk_mq_hw_ctx,
|
||||
kobj);
|
||||
|
||||
if (hctx->flags & BLK_MQ_F_BLOCKING)
|
||||
cleanup_srcu_struct(hctx->srcu);
|
||||
blk_free_flush_queue(hctx->fq);
|
||||
sbitmap_free(&hctx->ctx_map);
|
||||
free_cpumask_var(hctx->cpumask);
|
||||
kfree(hctx->ctxs);
|
||||
kfree(hctx);
|
||||
|
||||
@ -2157,12 +2157,7 @@ static void blk_mq_exit_hctx(struct request_queue *q,
|
||||
if (set->ops->exit_hctx)
|
||||
set->ops->exit_hctx(hctx, hctx_idx);
|
||||
|
||||
if (hctx->flags & BLK_MQ_F_BLOCKING)
|
||||
cleanup_srcu_struct(hctx->srcu);
|
||||
|
||||
blk_mq_remove_cpuhp(hctx);
|
||||
blk_free_flush_queue(hctx->fq);
|
||||
sbitmap_free(&hctx->ctx_map);
|
||||
}
|
||||
|
||||
static void blk_mq_exit_hw_queues(struct request_queue *q,
|
||||
@ -2662,7 +2657,8 @@ err_exit:
|
||||
}
|
||||
EXPORT_SYMBOL(blk_mq_init_allocated_queue);
|
||||
|
||||
void blk_mq_free_queue(struct request_queue *q)
|
||||
/* tags can _not_ be used after returning from blk_mq_exit_queue */
|
||||
void blk_mq_exit_queue(struct request_queue *q)
|
||||
{
|
||||
struct blk_mq_tag_set *set = q->tag_set;
|
||||
|
||||
|
||||
@ -31,7 +31,7 @@ struct blk_mq_ctx {
|
||||
} ____cacheline_aligned_in_smp;
|
||||
|
||||
void blk_mq_freeze_queue(struct request_queue *q);
|
||||
void blk_mq_free_queue(struct request_queue *q);
|
||||
void blk_mq_exit_queue(struct request_queue *q);
|
||||
int blk_mq_update_nr_requests(struct request_queue *q, unsigned int nr);
|
||||
void blk_mq_wake_waiters(struct request_queue *q);
|
||||
bool blk_mq_dispatch_rq_list(struct request_queue *, struct list_head *, bool);
|
||||
|
||||
@ -33,7 +33,7 @@
|
||||
|
||||
struct st33zp24_i2c_phy {
|
||||
struct i2c_client *client;
|
||||
u8 buf[TPM_BUFSIZE + 1];
|
||||
u8 buf[ST33ZP24_BUFSIZE + 1];
|
||||
int io_lpcpd;
|
||||
};
|
||||
|
||||
|
||||
@ -63,7 +63,7 @@
|
||||
* some latency byte before the answer is available (max 15).
|
||||
* We have 2048 + 1024 + 15.
|
||||
*/
|
||||
#define ST33ZP24_SPI_BUFFER_SIZE (TPM_BUFSIZE + (TPM_BUFSIZE / 2) +\
|
||||
#define ST33ZP24_SPI_BUFFER_SIZE (ST33ZP24_BUFSIZE + (ST33ZP24_BUFSIZE / 2) +\
|
||||
MAX_SPI_LATENCY)
|
||||
|
||||
|
||||
|
||||
@ -18,8 +18,8 @@
|
||||
#ifndef __LOCAL_ST33ZP24_H__
|
||||
#define __LOCAL_ST33ZP24_H__
|
||||
|
||||
#define TPM_WRITE_DIRECTION 0x80
|
||||
#define TPM_BUFSIZE 2048
|
||||
#define TPM_WRITE_DIRECTION 0x80
|
||||
#define ST33ZP24_BUFSIZE 2048
|
||||
|
||||
struct st33zp24_dev {
|
||||
struct tpm_chip *chip;
|
||||
|
||||
@ -26,8 +26,7 @@
|
||||
#include <linux/wait.h>
|
||||
#include "tpm.h"
|
||||
|
||||
/* max. buffer size supported by our TPM */
|
||||
#define TPM_BUFSIZE 1260
|
||||
#define TPM_I2C_INFINEON_BUFSIZE 1260
|
||||
|
||||
/* max. number of iterations after I2C NAK */
|
||||
#define MAX_COUNT 3
|
||||
@ -63,11 +62,13 @@ enum i2c_chip_type {
|
||||
UNKNOWN,
|
||||
};
|
||||
|
||||
/* Structure to store I2C TPM specific stuff */
|
||||
struct tpm_inf_dev {
|
||||
struct i2c_client *client;
|
||||
int locality;
|
||||
u8 buf[TPM_BUFSIZE + sizeof(u8)]; /* max. buffer size + addr */
|
||||
/* In addition to the data itself, the buffer must fit the 7-bit I2C
|
||||
* address and the direction bit.
|
||||
*/
|
||||
u8 buf[TPM_I2C_INFINEON_BUFSIZE + 1];
|
||||
struct tpm_chip *chip;
|
||||
enum i2c_chip_type chip_type;
|
||||
unsigned int adapterlimit;
|
||||
@ -219,7 +220,7 @@ static int iic_tpm_write_generic(u8 addr, u8 *buffer, size_t len,
|
||||
.buf = tpm_dev.buf
|
||||
};
|
||||
|
||||
if (len > TPM_BUFSIZE)
|
||||
if (len > TPM_I2C_INFINEON_BUFSIZE)
|
||||
return -EINVAL;
|
||||
|
||||
if (!tpm_dev.client->adapter->algo->master_xfer)
|
||||
@ -527,8 +528,8 @@ static int tpm_tis_i2c_send(struct tpm_chip *chip, u8 *buf, size_t len)
|
||||
u8 retries = 0;
|
||||
u8 sts = TPM_STS_GO;
|
||||
|
||||
if (len > TPM_BUFSIZE)
|
||||
return -E2BIG; /* command is too long for our tpm, sorry */
|
||||
if (len > TPM_I2C_INFINEON_BUFSIZE)
|
||||
return -E2BIG;
|
||||
|
||||
if (request_locality(chip, 0) < 0)
|
||||
return -EBUSY;
|
||||
|
||||
@ -35,14 +35,12 @@
|
||||
#include "tpm.h"
|
||||
|
||||
/* I2C interface offsets */
|
||||
#define TPM_STS 0x00
|
||||
#define TPM_BURST_COUNT 0x01
|
||||
#define TPM_DATA_FIFO_W 0x20
|
||||
#define TPM_DATA_FIFO_R 0x40
|
||||
#define TPM_VID_DID_RID 0x60
|
||||
/* TPM command header size */
|
||||
#define TPM_HEADER_SIZE 10
|
||||
#define TPM_RETRY 5
|
||||
#define TPM_STS 0x00
|
||||
#define TPM_BURST_COUNT 0x01
|
||||
#define TPM_DATA_FIFO_W 0x20
|
||||
#define TPM_DATA_FIFO_R 0x40
|
||||
#define TPM_VID_DID_RID 0x60
|
||||
#define TPM_I2C_RETRIES 5
|
||||
/*
|
||||
* I2C bus device maximum buffer size w/o counting I2C address or command
|
||||
* i.e. max size required for I2C write is 34 = addr, command, 32 bytes data
|
||||
@ -292,7 +290,7 @@ static int i2c_nuvoton_recv(struct tpm_chip *chip, u8 *buf, size_t count)
|
||||
dev_err(dev, "%s() count < header size\n", __func__);
|
||||
return -EIO;
|
||||
}
|
||||
for (retries = 0; retries < TPM_RETRY; retries++) {
|
||||
for (retries = 0; retries < TPM_I2C_RETRIES; retries++) {
|
||||
if (retries > 0) {
|
||||
/* if this is not the first trial, set responseRetry */
|
||||
i2c_nuvoton_write_status(client,
|
||||
|
||||
@ -255,7 +255,7 @@ MODULE_DEVICE_TABLE(platform, s2mps11_clk_id);
|
||||
* This requires of_device_id table. In the same time this will not change the
|
||||
* actual *device* matching so do not add .of_match_table.
|
||||
*/
|
||||
static const struct of_device_id s2mps11_dt_match[] = {
|
||||
static const struct of_device_id s2mps11_dt_match[] __used = {
|
||||
{
|
||||
.compatible = "samsung,s2mps11-clk",
|
||||
.data = (void *)S2MPS11X,
|
||||
|
||||
@ -55,7 +55,7 @@ const struct clk_ops tegra_clk_sync_source_ops = {
|
||||
};
|
||||
|
||||
struct clk *tegra_clk_register_sync_source(const char *name,
|
||||
unsigned long rate, unsigned long max_rate)
|
||||
unsigned long max_rate)
|
||||
{
|
||||
struct tegra_clk_sync_source *sync;
|
||||
struct clk_init_data init;
|
||||
@ -67,7 +67,6 @@ struct clk *tegra_clk_register_sync_source(const char *name,
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
sync->rate = rate;
|
||||
sync->max_rate = max_rate;
|
||||
|
||||
init.ops = &tegra_clk_sync_source_ops;
|
||||
|
||||
@ -49,8 +49,6 @@ struct tegra_sync_source_initdata {
|
||||
#define SYNC(_name) \
|
||||
{\
|
||||
.name = #_name,\
|
||||
.rate = 24000000,\
|
||||
.max_rate = 24000000,\
|
||||
.clk_id = tegra_clk_ ## _name,\
|
||||
}
|
||||
|
||||
@ -176,7 +174,7 @@ static void __init tegra_audio_sync_clk_init(void __iomem *clk_base,
|
||||
void __init tegra_audio_clk_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
|
||||
struct tegra_audio_clk_info *audio_info,
|
||||
unsigned int num_plls)
|
||||
unsigned int num_plls, unsigned long sync_max_rate)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk **dt_clk;
|
||||
@ -221,8 +219,7 @@ void __init tegra_audio_clk_init(void __iomem *clk_base,
|
||||
if (!dt_clk)
|
||||
continue;
|
||||
|
||||
clk = tegra_clk_register_sync_source(data->name,
|
||||
data->rate, data->max_rate);
|
||||
clk = tegra_clk_register_sync_source(data->name, sync_max_rate);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
|
||||
@ -1190,6 +1190,13 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
||||
{ TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
|
||||
{ TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },
|
||||
{ TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_I2S2_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
@ -1362,7 +1369,7 @@ static void __init tegra114_clock_init(struct device_node *np)
|
||||
tegra114_periph_clk_init(clk_base, pmc_base);
|
||||
tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
|
||||
tegra114_audio_plls,
|
||||
ARRAY_SIZE(tegra114_audio_plls));
|
||||
ARRAY_SIZE(tegra114_audio_plls), 24000000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra114_clks);
|
||||
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
|
||||
&pll_x_params);
|
||||
|
||||
@ -1291,6 +1291,13 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
|
||||
{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
|
||||
{ TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },
|
||||
{ TEGRA124_CLK_SPDIF_IN_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_I2S0_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_I2S1_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_I2S2_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
@ -1455,7 +1462,7 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
|
||||
tegra124_periph_clk_init(clk_base, pmc_base);
|
||||
tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
|
||||
tegra124_audio_plls,
|
||||
ARRAY_SIZE(tegra124_audio_plls));
|
||||
ARRAY_SIZE(tegra124_audio_plls), 24576000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra124_clks);
|
||||
|
||||
/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
|
||||
|
||||
@ -3369,6 +3369,15 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
||||
{ TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
|
||||
{ TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
|
||||
{ TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
|
||||
{ TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
|
||||
{ TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
|
||||
/* This MUST be the last entry. */
|
||||
{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
@ -3562,7 +3571,7 @@ static void __init tegra210_clock_init(struct device_node *np)
|
||||
tegra210_periph_clk_init(clk_base, pmc_base);
|
||||
tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
|
||||
tegra210_audio_plls,
|
||||
ARRAY_SIZE(tegra210_audio_plls));
|
||||
ARRAY_SIZE(tegra210_audio_plls), 24576000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra210_clks);
|
||||
|
||||
/* For Tegra210, PLLD is the only source for DSIA & DSIB */
|
||||
|
||||
@ -1267,6 +1267,13 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
||||
{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
|
||||
{ TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
|
||||
{ TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
|
||||
{ TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_I2S2_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
{ TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
@ -1344,7 +1351,7 @@ static void __init tegra30_clock_init(struct device_node *np)
|
||||
tegra30_periph_clk_init();
|
||||
tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
|
||||
tegra30_audio_plls,
|
||||
ARRAY_SIZE(tegra30_audio_plls));
|
||||
ARRAY_SIZE(tegra30_audio_plls), 24000000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra30_clks);
|
||||
|
||||
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
|
||||
|
||||
@ -41,7 +41,7 @@ extern const struct clk_ops tegra_clk_sync_source_ops;
|
||||
extern int *periph_clk_enb_refcnt;
|
||||
|
||||
struct clk *tegra_clk_register_sync_source(const char *name,
|
||||
unsigned long fixed_rate, unsigned long max_rate);
|
||||
unsigned long max_rate);
|
||||
|
||||
/**
|
||||
* struct tegra_clk_frac_div - fractional divider clock
|
||||
@ -796,7 +796,7 @@ void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
|
||||
void tegra_audio_clk_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
|
||||
struct tegra_audio_clk_info *audio_info,
|
||||
unsigned int num_plls);
|
||||
unsigned int num_plls, unsigned long sync_max_rate);
|
||||
|
||||
void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks,
|
||||
|
||||
@ -364,7 +364,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
|
||||
rc = cc_ivgen_init(new_drvdata);
|
||||
if (rc) {
|
||||
dev_err(dev, "cc_ivgen_init failed\n");
|
||||
goto post_power_mgr_err;
|
||||
goto post_buf_mgr_err;
|
||||
}
|
||||
|
||||
/* Allocate crypto algs */
|
||||
@ -387,6 +387,9 @@ static int init_cc_resources(struct platform_device *plat_dev)
|
||||
goto post_hash_err;
|
||||
}
|
||||
|
||||
/* All set, we can allow autosuspend */
|
||||
cc_pm_go(new_drvdata);
|
||||
|
||||
/* If we got here and FIPS mode is enabled
|
||||
* it means all FIPS test passed, so let TEE
|
||||
* know we're good.
|
||||
@ -401,8 +404,6 @@ post_cipher_err:
|
||||
cc_cipher_free(new_drvdata);
|
||||
post_ivgen_err:
|
||||
cc_ivgen_fini(new_drvdata);
|
||||
post_power_mgr_err:
|
||||
cc_pm_fini(new_drvdata);
|
||||
post_buf_mgr_err:
|
||||
cc_buffer_mgr_fini(new_drvdata);
|
||||
post_req_mgr_err:
|
||||
|
||||
@ -103,20 +103,19 @@ int cc_pm_put_suspend(struct device *dev)
|
||||
|
||||
int cc_pm_init(struct cc_drvdata *drvdata)
|
||||
{
|
||||
int rc = 0;
|
||||
struct device *dev = drvdata_to_dev(drvdata);
|
||||
|
||||
/* must be before the enabling to avoid resdundent suspending */
|
||||
pm_runtime_set_autosuspend_delay(dev, CC_SUSPEND_TIMEOUT);
|
||||
pm_runtime_use_autosuspend(dev);
|
||||
/* activate the PM module */
|
||||
rc = pm_runtime_set_active(dev);
|
||||
if (rc)
|
||||
return rc;
|
||||
/* enable the PM module*/
|
||||
pm_runtime_enable(dev);
|
||||
return pm_runtime_set_active(dev);
|
||||
}
|
||||
|
||||
return rc;
|
||||
/* enable the PM module*/
|
||||
void cc_pm_go(struct cc_drvdata *drvdata)
|
||||
{
|
||||
pm_runtime_enable(drvdata_to_dev(drvdata));
|
||||
}
|
||||
|
||||
void cc_pm_fini(struct cc_drvdata *drvdata)
|
||||
|
||||
@ -16,6 +16,7 @@
|
||||
extern const struct dev_pm_ops ccree_pm;
|
||||
|
||||
int cc_pm_init(struct cc_drvdata *drvdata);
|
||||
void cc_pm_go(struct cc_drvdata *drvdata);
|
||||
void cc_pm_fini(struct cc_drvdata *drvdata);
|
||||
int cc_pm_suspend(struct device *dev);
|
||||
int cc_pm_resume(struct device *dev);
|
||||
@ -29,6 +30,8 @@ static inline int cc_pm_init(struct cc_drvdata *drvdata)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void cc_pm_go(struct cc_drvdata *drvdata) {}
|
||||
|
||||
static inline void cc_pm_fini(struct cc_drvdata *drvdata) {}
|
||||
|
||||
static inline int cc_pm_suspend(struct device *dev)
|
||||
|
||||
@ -1070,7 +1070,7 @@ void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
|
||||
int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
|
||||
{
|
||||
struct amdgpu_device *adev = ring->adev;
|
||||
uint32_t rptr = amdgpu_ring_get_rptr(ring);
|
||||
uint32_t rptr;
|
||||
unsigned i;
|
||||
int r, timeout = adev->usec_timeout;
|
||||
|
||||
@ -1084,6 +1084,9 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
|
||||
ring->idx, r);
|
||||
return r;
|
||||
}
|
||||
|
||||
rptr = amdgpu_ring_get_rptr(ring);
|
||||
|
||||
amdgpu_ring_write(ring, VCE_CMD_END);
|
||||
amdgpu_ring_commit(ring);
|
||||
|
||||
|
||||
@ -431,7 +431,7 @@ error:
|
||||
int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
|
||||
{
|
||||
struct amdgpu_device *adev = ring->adev;
|
||||
uint32_t rptr = amdgpu_ring_get_rptr(ring);
|
||||
uint32_t rptr;
|
||||
unsigned i;
|
||||
int r;
|
||||
|
||||
@ -441,6 +441,9 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
|
||||
ring->idx, r);
|
||||
return r;
|
||||
}
|
||||
|
||||
rptr = amdgpu_ring_get_rptr(ring);
|
||||
|
||||
amdgpu_ring_write(ring, VCN_ENC_CMD_END);
|
||||
amdgpu_ring_commit(ring);
|
||||
|
||||
|
||||
@ -82,7 +82,8 @@ MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
|
||||
|
||||
static const struct soc15_reg_golden golden_settings_gc_9_0[] =
|
||||
{
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
|
||||
|
||||
@ -170,7 +170,7 @@ static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
|
||||
static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
|
||||
{
|
||||
struct amdgpu_device *adev = ring->adev;
|
||||
uint32_t rptr = amdgpu_ring_get_rptr(ring);
|
||||
uint32_t rptr;
|
||||
unsigned i;
|
||||
int r;
|
||||
|
||||
@ -180,6 +180,9 @@ static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
|
||||
ring->idx, r);
|
||||
return r;
|
||||
}
|
||||
|
||||
rptr = amdgpu_ring_get_rptr(ring);
|
||||
|
||||
amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
|
||||
amdgpu_ring_commit(ring);
|
||||
|
||||
|
||||
@ -175,7 +175,7 @@ static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
|
||||
static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
|
||||
{
|
||||
struct amdgpu_device *adev = ring->adev;
|
||||
uint32_t rptr = amdgpu_ring_get_rptr(ring);
|
||||
uint32_t rptr;
|
||||
unsigned i;
|
||||
int r;
|
||||
|
||||
@ -188,6 +188,9 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
|
||||
ring->me, ring->idx, r);
|
||||
return r;
|
||||
}
|
||||
|
||||
rptr = amdgpu_ring_get_rptr(ring);
|
||||
|
||||
amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
|
||||
amdgpu_ring_commit(ring);
|
||||
|
||||
|
||||
@ -310,6 +310,7 @@ static const struct kfd_deviceid supported_devices[] = {
|
||||
{ 0x67CF, &polaris10_device_info }, /* Polaris10 */
|
||||
{ 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/
|
||||
{ 0x67DF, &polaris10_device_info }, /* Polaris10 */
|
||||
{ 0x6FDF, &polaris10_device_info }, /* Polaris10 */
|
||||
{ 0x67E0, &polaris11_device_info }, /* Polaris11 */
|
||||
{ 0x67E1, &polaris11_device_info }, /* Polaris11 */
|
||||
{ 0x67E3, &polaris11_device_info }, /* Polaris11 */
|
||||
|
||||
@ -377,9 +377,6 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
|
||||
drm_connector_attach_encoder(&aconnector->base,
|
||||
&aconnector->mst_encoder->base);
|
||||
|
||||
/*
|
||||
* TODO: understand why this one is needed
|
||||
*/
|
||||
drm_object_attach_property(
|
||||
&connector->base,
|
||||
dev->mode_config.path_property,
|
||||
|
||||
@ -669,20 +669,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
|
||||
for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
|
||||
table->WatermarkRow[1][i].MinClock =
|
||||
cpu_to_le16((uint16_t)
|
||||
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
|
||||
1000);
|
||||
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
|
||||
1000));
|
||||
table->WatermarkRow[1][i].MaxClock =
|
||||
cpu_to_le16((uint16_t)
|
||||
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
|
||||
100);
|
||||
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
|
||||
1000));
|
||||
table->WatermarkRow[1][i].MinUclk =
|
||||
cpu_to_le16((uint16_t)
|
||||
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
|
||||
1000);
|
||||
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
|
||||
1000));
|
||||
table->WatermarkRow[1][i].MaxUclk =
|
||||
cpu_to_le16((uint16_t)
|
||||
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
|
||||
1000);
|
||||
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
|
||||
1000));
|
||||
table->WatermarkRow[1][i].WmSetting = (uint8_t)
|
||||
wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
|
||||
}
|
||||
@ -690,20 +690,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
|
||||
for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {
|
||||
table->WatermarkRow[0][i].MinClock =
|
||||
cpu_to_le16((uint16_t)
|
||||
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) /
|
||||
1000);
|
||||
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
|
||||
1000));
|
||||
table->WatermarkRow[0][i].MaxClock =
|
||||
cpu_to_le16((uint16_t)
|
||||
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) /
|
||||
1000);
|
||||
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
|
||||
1000));
|
||||
table->WatermarkRow[0][i].MinUclk =
|
||||
cpu_to_le16((uint16_t)
|
||||
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
|
||||
1000);
|
||||
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
|
||||
1000));
|
||||
table->WatermarkRow[0][i].MaxUclk =
|
||||
cpu_to_le16((uint16_t)
|
||||
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
|
||||
1000);
|
||||
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
|
||||
1000));
|
||||
table->WatermarkRow[0][i].WmSetting = (uint8_t)
|
||||
wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
|
||||
}
|
||||
|
||||
@ -1702,6 +1702,27 @@ drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
|
||||
struct drm_connector *connector = conn_state->connector;
|
||||
struct drm_crtc_state *crtc_state;
|
||||
|
||||
/*
|
||||
* For compatibility with legacy users, we want to make sure that
|
||||
* we allow DPMS On<->Off modesets on unregistered connectors, since
|
||||
* legacy modesetting users will not be expecting these to fail. We do
|
||||
* not however, want to allow legacy users to assign a connector
|
||||
* that's been unregistered from sysfs to another CRTC, since doing
|
||||
* this with a now non-existent connector could potentially leave us
|
||||
* in an invalid state.
|
||||
*
|
||||
* Since the connector can be unregistered at any point during an
|
||||
* atomic check or commit, this is racy. But that's OK: all we care
|
||||
* about is ensuring that userspace can't use this connector for new
|
||||
* configurations after it's been notified that the connector is no
|
||||
* longer present.
|
||||
*/
|
||||
if (!READ_ONCE(connector->registered) && crtc) {
|
||||
DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] is not registered\n",
|
||||
connector->base.id, connector->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (conn_state->crtc == crtc)
|
||||
return 0;
|
||||
|
||||
|
||||
@ -185,7 +185,7 @@ static int compat_drm_getmap(struct file *file, unsigned int cmd,
|
||||
m32.size = map.size;
|
||||
m32.type = map.type;
|
||||
m32.flags = map.flags;
|
||||
m32.handle = ptr_to_compat(map.handle);
|
||||
m32.handle = ptr_to_compat((void __user *)map.handle);
|
||||
m32.mtrr = map.mtrr;
|
||||
if (copy_to_user(argp, &m32, sizeof(m32)))
|
||||
return -EFAULT;
|
||||
@ -216,7 +216,7 @@ static int compat_drm_addmap(struct file *file, unsigned int cmd,
|
||||
|
||||
m32.offset = map.offset;
|
||||
m32.mtrr = map.mtrr;
|
||||
m32.handle = ptr_to_compat(map.handle);
|
||||
m32.handle = ptr_to_compat((void __user *)map.handle);
|
||||
if (map.handle != compat_ptr(m32.handle))
|
||||
pr_err_ratelimited("compat_drm_addmap truncated handle %p for type %d offset %x\n",
|
||||
map.handle, m32.type, m32.offset);
|
||||
@ -529,7 +529,7 @@ static int compat_drm_getsareactx(struct file *file, unsigned int cmd,
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
req32.handle = ptr_to_compat(req.handle);
|
||||
req32.handle = ptr_to_compat((void __user *)req.handle);
|
||||
if (copy_to_user(argp, &req32, sizeof(req32)))
|
||||
return -EFAULT;
|
||||
|
||||
|
||||
@ -105,13 +105,20 @@ static void store_vblank(struct drm_device *dev, unsigned int pipe,
|
||||
write_sequnlock(&vblank->seqlock);
|
||||
}
|
||||
|
||||
static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe)
|
||||
{
|
||||
struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
|
||||
|
||||
return vblank->max_vblank_count ?: dev->max_vblank_count;
|
||||
}
|
||||
|
||||
/*
|
||||
* "No hw counter" fallback implementation of .get_vblank_counter() hook,
|
||||
* if there is no useable hardware frame counter available.
|
||||
*/
|
||||
static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe)
|
||||
{
|
||||
WARN_ON_ONCE(dev->max_vblank_count != 0);
|
||||
WARN_ON_ONCE(drm_max_vblank_count(dev, pipe) != 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -198,6 +205,7 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe,
|
||||
ktime_t t_vblank;
|
||||
int count = DRM_TIMESTAMP_MAXRETRIES;
|
||||
int framedur_ns = vblank->framedur_ns;
|
||||
u32 max_vblank_count = drm_max_vblank_count(dev, pipe);
|
||||
|
||||
/*
|
||||
* Interrupts were disabled prior to this call, so deal with counter
|
||||
@ -216,9 +224,9 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe,
|
||||
rc = drm_get_last_vbltimestamp(dev, pipe, &t_vblank, in_vblank_irq);
|
||||
} while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);
|
||||
|
||||
if (dev->max_vblank_count != 0) {
|
||||
if (max_vblank_count) {
|
||||
/* trust the hw counter when it's around */
|
||||
diff = (cur_vblank - vblank->last) & dev->max_vblank_count;
|
||||
diff = (cur_vblank - vblank->last) & max_vblank_count;
|
||||
} else if (rc && framedur_ns) {
|
||||
u64 diff_ns = ktime_to_ns(ktime_sub(t_vblank, vblank->time));
|
||||
|
||||
@ -1204,6 +1212,37 @@ void drm_crtc_vblank_reset(struct drm_crtc *crtc)
|
||||
}
|
||||
EXPORT_SYMBOL(drm_crtc_vblank_reset);
|
||||
|
||||
/**
|
||||
* drm_crtc_set_max_vblank_count - configure the hw max vblank counter value
|
||||
* @crtc: CRTC in question
|
||||
* @max_vblank_count: max hardware vblank counter value
|
||||
*
|
||||
* Update the maximum hardware vblank counter value for @crtc
|
||||
* at runtime. Useful for hardware where the operation of the
|
||||
* hardware vblank counter depends on the currently active
|
||||
* display configuration.
|
||||
*
|
||||
* For example, if the hardware vblank counter does not work
|
||||
* when a specific connector is active the maximum can be set
|
||||
* to zero. And when that specific connector isn't active the
|
||||
* maximum can again be set to the appropriate non-zero value.
|
||||
*
|
||||
* If used, must be called before drm_vblank_on().
|
||||
*/
|
||||
void drm_crtc_set_max_vblank_count(struct drm_crtc *crtc,
|
||||
u32 max_vblank_count)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
unsigned int pipe = drm_crtc_index(crtc);
|
||||
struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
|
||||
|
||||
WARN_ON(dev->max_vblank_count);
|
||||
WARN_ON(!READ_ONCE(vblank->inmodeset));
|
||||
|
||||
vblank->max_vblank_count = max_vblank_count;
|
||||
}
|
||||
EXPORT_SYMBOL(drm_crtc_set_max_vblank_count);
|
||||
|
||||
/**
|
||||
* drm_crtc_vblank_on - enable vblank events on a CRTC
|
||||
* @crtc: CRTC in question
|
||||
|
||||
@ -1788,6 +1788,8 @@ static int i915_emon_status(struct seq_file *m, void *unused)
|
||||
if (!IS_GEN5(dev_priv))
|
||||
return -ENODEV;
|
||||
|
||||
intel_runtime_pm_get(dev_priv);
|
||||
|
||||
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -1802,6 +1804,8 @@ static int i915_emon_status(struct seq_file *m, void *unused)
|
||||
seq_printf(m, "GFX power: %ld\n", gfx);
|
||||
seq_printf(m, "Total power: %ld\n", chipset + gfx);
|
||||
|
||||
intel_runtime_pm_put(dev_priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -1874,20 +1874,28 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
|
||||
* pages from.
|
||||
*/
|
||||
if (!obj->base.filp) {
|
||||
i915_gem_object_put(obj);
|
||||
return -ENXIO;
|
||||
addr = -ENXIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (range_overflows(args->offset, args->size, (u64)obj->base.size)) {
|
||||
addr = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
addr = vm_mmap(obj->base.filp, 0, args->size,
|
||||
PROT_READ | PROT_WRITE, MAP_SHARED,
|
||||
args->offset);
|
||||
if (IS_ERR_VALUE(addr))
|
||||
goto err;
|
||||
|
||||
if (args->flags & I915_MMAP_WC) {
|
||||
struct mm_struct *mm = current->mm;
|
||||
struct vm_area_struct *vma;
|
||||
|
||||
if (down_write_killable(&mm->mmap_sem)) {
|
||||
i915_gem_object_put(obj);
|
||||
return -EINTR;
|
||||
addr = -EINTR;
|
||||
goto err;
|
||||
}
|
||||
vma = find_vma(mm, addr);
|
||||
if (vma && __vma_matches(vma, obj->base.filp, addr, args->size))
|
||||
@ -1896,17 +1904,20 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
|
||||
else
|
||||
addr = -ENOMEM;
|
||||
up_write(&mm->mmap_sem);
|
||||
if (IS_ERR_VALUE(addr))
|
||||
goto err;
|
||||
|
||||
/* This may race, but that's ok, it only gets set */
|
||||
WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
|
||||
}
|
||||
i915_gem_object_put(obj);
|
||||
if (IS_ERR((void *)addr))
|
||||
return addr;
|
||||
|
||||
args->addr_ptr = (uint64_t) addr;
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
i915_gem_object_put(obj);
|
||||
return addr;
|
||||
}
|
||||
|
||||
static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
|
||||
@ -5595,6 +5606,8 @@ err_uc_misc:
|
||||
i915_gem_cleanup_userptr(dev_priv);
|
||||
|
||||
if (ret == -EIO) {
|
||||
mutex_lock(&dev_priv->drm.struct_mutex);
|
||||
|
||||
/*
|
||||
* Allow engine initialisation to fail by marking the GPU as
|
||||
* wedged. But we only want to do this where the GPU is angry,
|
||||
@ -5605,7 +5618,14 @@ err_uc_misc:
|
||||
"Failed to initialize GPU, declaring it wedged!\n");
|
||||
i915_gem_set_wedged(dev_priv);
|
||||
}
|
||||
ret = 0;
|
||||
|
||||
/* Minimal basic recovery for KMS */
|
||||
ret = i915_ggtt_enable_hw(dev_priv);
|
||||
i915_gem_restore_gtt_mappings(dev_priv);
|
||||
i915_gem_restore_fences(dev_priv);
|
||||
intel_init_clock_gating(dev_priv);
|
||||
|
||||
mutex_unlock(&dev_priv->drm.struct_mutex);
|
||||
}
|
||||
|
||||
i915_gem_drain_freed_objects(dev_priv);
|
||||
@ -5615,6 +5635,7 @@ err_uc_misc:
|
||||
void i915_gem_fini(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
i915_gem_suspend_late(dev_priv);
|
||||
intel_disable_gt_powersave(dev_priv);
|
||||
|
||||
/* Flush any outstanding unpin_work. */
|
||||
i915_gem_drain_workqueue(dev_priv);
|
||||
@ -5626,6 +5647,8 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
|
||||
i915_gem_contexts_fini(dev_priv);
|
||||
mutex_unlock(&dev_priv->drm.struct_mutex);
|
||||
|
||||
intel_cleanup_gt_powersave(dev_priv);
|
||||
|
||||
intel_uc_fini_misc(dev_priv);
|
||||
i915_gem_cleanup_userptr(dev_priv);
|
||||
|
||||
|
||||
@ -6531,7 +6531,7 @@ enum {
|
||||
#define PLANE_CTL_YUV422_UYVY (1 << 16)
|
||||
#define PLANE_CTL_YUV422_YVYU (2 << 16)
|
||||
#define PLANE_CTL_YUV422_VYUY (3 << 16)
|
||||
#define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
|
||||
#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
|
||||
#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
|
||||
#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
|
||||
#define PLANE_CTL_TILED_MASK (0x7 << 10)
|
||||
|
||||
@ -2208,6 +2208,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
|
||||
if (INTEL_GEN(dev_priv) >= 9)
|
||||
min_cdclk = max(2 * 96000, min_cdclk);
|
||||
|
||||
/*
|
||||
* "For DP audio configuration, cdclk frequency shall be set to
|
||||
* meet the following requirements:
|
||||
* DP Link Frequency(MHz) | Cdclk frequency(MHz)
|
||||
* 270 | 320 or higher
|
||||
* 162 | 200 or higher"
|
||||
*/
|
||||
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
|
||||
intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
|
||||
min_cdclk = max(crtc_state->port_clock, min_cdclk);
|
||||
|
||||
/*
|
||||
* On Valleyview some DSI panels lose (v|h)sync when the clock is lower
|
||||
* than 320000KHz.
|
||||
|
||||
@ -2712,6 +2712,17 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
|
||||
if (size_aligned * 2 > dev_priv->stolen_usable_size)
|
||||
return false;
|
||||
|
||||
switch (fb->modifier) {
|
||||
case DRM_FORMAT_MOD_LINEAR:
|
||||
case I915_FORMAT_MOD_X_TILED:
|
||||
case I915_FORMAT_MOD_Y_TILED:
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
|
||||
fb->modifier);
|
||||
return false;
|
||||
}
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
|
||||
base_aligned,
|
||||
@ -2721,8 +2732,17 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
|
||||
if (!obj)
|
||||
return false;
|
||||
|
||||
if (plane_config->tiling == I915_TILING_X)
|
||||
obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
|
||||
switch (plane_config->tiling) {
|
||||
case I915_TILING_NONE:
|
||||
break;
|
||||
case I915_TILING_X:
|
||||
case I915_TILING_Y:
|
||||
obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
|
||||
break;
|
||||
default:
|
||||
MISSING_CASE(plane_config->tiling);
|
||||
return false;
|
||||
}
|
||||
|
||||
mode_cmd.pixel_format = fb->format->format;
|
||||
mode_cmd.width = fb->width;
|
||||
@ -3561,11 +3581,11 @@ static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
|
||||
case I915_FORMAT_MOD_Y_TILED:
|
||||
return PLANE_CTL_TILED_Y;
|
||||
case I915_FORMAT_MOD_Y_TILED_CCS:
|
||||
return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
|
||||
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
|
||||
case I915_FORMAT_MOD_Yf_TILED:
|
||||
return PLANE_CTL_TILED_YF;
|
||||
case I915_FORMAT_MOD_Yf_TILED_CCS:
|
||||
return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
|
||||
return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
|
||||
default:
|
||||
MISSING_CASE(fb_modifier);
|
||||
}
|
||||
@ -8812,13 +8832,14 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
|
||||
fb->modifier = I915_FORMAT_MOD_X_TILED;
|
||||
break;
|
||||
case PLANE_CTL_TILED_Y:
|
||||
if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
|
||||
plane_config->tiling = I915_TILING_Y;
|
||||
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
|
||||
fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
|
||||
else
|
||||
fb->modifier = I915_FORMAT_MOD_Y_TILED;
|
||||
break;
|
||||
case PLANE_CTL_TILED_YF:
|
||||
if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
|
||||
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
|
||||
fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
|
||||
else
|
||||
fb->modifier = I915_FORMAT_MOD_Yf_TILED;
|
||||
@ -15951,8 +15972,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
|
||||
flush_work(&dev_priv->atomic_helper.free_work);
|
||||
WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
|
||||
|
||||
intel_disable_gt_powersave(dev_priv);
|
||||
|
||||
/*
|
||||
* Interrupts and polling as the first thing to avoid creating havoc.
|
||||
* Too much stuff here (turning of connectors, ...) would
|
||||
@ -15980,8 +15999,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
|
||||
|
||||
intel_cleanup_overlay(dev_priv);
|
||||
|
||||
intel_cleanup_gt_powersave(dev_priv);
|
||||
|
||||
intel_teardown_gmbus(dev_priv);
|
||||
|
||||
destroy_workqueue(dev_priv->modeset_wq);
|
||||
|
||||
@ -4739,6 +4739,22 @@ intel_dp_long_pulse(struct intel_connector *connector,
|
||||
*/
|
||||
status = connector_status_disconnected;
|
||||
goto out;
|
||||
} else {
|
||||
/*
|
||||
* If display is now connected check links status,
|
||||
* there has been known issues of link loss triggering
|
||||
* long pulse.
|
||||
*
|
||||
* Some sinks (eg. ASUS PB287Q) seem to perform some
|
||||
* weird HPD ping pong during modesets. So we can apparently
|
||||
* end up with HPD going low during a modeset, and then
|
||||
* going back up soon after. And once that happens we must
|
||||
* retrain the link to get a picture. That's in case no
|
||||
* userspace component reacted to intermittent HPD dip.
|
||||
*/
|
||||
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
||||
|
||||
intel_dp_retrain_link(encoder, ctx);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -408,8 +408,6 @@ static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *c
|
||||
struct intel_dp *intel_dp = intel_connector->mst_port;
|
||||
struct intel_crtc *crtc = to_intel_crtc(state->crtc);
|
||||
|
||||
if (!READ_ONCE(connector->registered))
|
||||
return NULL;
|
||||
return &intel_dp->mst_encoders[crtc->pipe]->base.base;
|
||||
}
|
||||
|
||||
|
||||
@ -759,7 +759,8 @@ nv50_msto_enable(struct drm_encoder *encoder)
|
||||
|
||||
slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
|
||||
r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
|
||||
WARN_ON(!r);
|
||||
if (!r)
|
||||
DRM_DEBUG_KMS("Failed to allocate VCPI\n");
|
||||
|
||||
if (!mstm->links++)
|
||||
nv50_outp_acquire(mstm->outp);
|
||||
|
||||
@ -436,6 +436,32 @@ static const struct panel_desc ampire_am800480r3tmqwa1h = {
|
||||
.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
|
||||
};
|
||||
|
||||
static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
|
||||
.pixelclock = { 26400000, 33300000, 46800000 },
|
||||
.hactive = { 800, 800, 800 },
|
||||
.hfront_porch = { 16, 210, 354 },
|
||||
.hback_porch = { 45, 36, 6 },
|
||||
.hsync_len = { 1, 10, 40 },
|
||||
.vactive = { 480, 480, 480 },
|
||||
.vfront_porch = { 7, 22, 147 },
|
||||
.vback_porch = { 22, 13, 3 },
|
||||
.vsync_len = { 1, 10, 20 },
|
||||
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
|
||||
DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
|
||||
};
|
||||
|
||||
static const struct panel_desc armadeus_st0700_adapt = {
|
||||
.timings = &santek_st0700i5y_rbslw_f_timing,
|
||||
.num_timings = 1,
|
||||
.bpc = 6,
|
||||
.size = {
|
||||
.width = 154,
|
||||
.height = 86,
|
||||
},
|
||||
.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
|
||||
.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
|
||||
};
|
||||
|
||||
static const struct drm_display_mode auo_b101aw03_mode = {
|
||||
.clock = 51450,
|
||||
.hdisplay = 1024,
|
||||
@ -2330,6 +2356,9 @@ static const struct of_device_id platform_of_match[] = {
|
||||
}, {
|
||||
.compatible = "ampire,am800480r3tmqwa1h",
|
||||
.data = &ire_am800480r3tmqwa1h,
|
||||
}, {
|
||||
.compatible = "armadeus,st0700-adapt",
|
||||
.data = &armadeus_st0700_adapt,
|
||||
}, {
|
||||
.compatible = "auo,b101aw03",
|
||||
.data = &auo_b101aw03,
|
||||
|
||||
@ -353,7 +353,7 @@ static int vmw_recv_msg(struct rpc_channel *channel, void **msg,
|
||||
!!(HIGH_WORD(ecx) & MESSAGE_STATUS_HB));
|
||||
if ((HIGH_WORD(ebx) & MESSAGE_STATUS_SUCCESS) == 0) {
|
||||
kfree(reply);
|
||||
|
||||
reply = NULL;
|
||||
if ((HIGH_WORD(ebx) & MESSAGE_STATUS_CPT) != 0) {
|
||||
/* A checkpoint occurred. Retry. */
|
||||
continue;
|
||||
@ -377,7 +377,7 @@ static int vmw_recv_msg(struct rpc_channel *channel, void **msg,
|
||||
|
||||
if ((HIGH_WORD(ecx) & MESSAGE_STATUS_SUCCESS) == 0) {
|
||||
kfree(reply);
|
||||
|
||||
reply = NULL;
|
||||
if ((HIGH_WORD(ecx) & MESSAGE_STATUS_CPT) != 0) {
|
||||
/* A checkpoint occurred. Retry. */
|
||||
continue;
|
||||
@ -389,10 +389,8 @@ static int vmw_recv_msg(struct rpc_channel *channel, void **msg,
|
||||
break;
|
||||
}
|
||||
|
||||
if (retries == RETRIES) {
|
||||
kfree(reply);
|
||||
if (!reply)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
*msg_len = reply_len;
|
||||
*msg = reply;
|
||||
|
||||
@ -353,7 +353,9 @@ static void process_ib_ipinfo(void *in_msg, void *out_msg, int op)
|
||||
|
||||
out->body.kvp_ip_val.dhcp_enabled = in->kvp_ip_val.dhcp_enabled;
|
||||
|
||||
default:
|
||||
/* fallthrough */
|
||||
|
||||
case KVP_OP_GET_IP_INFO:
|
||||
utf16s_to_utf8s((wchar_t *)in->kvp_ip_val.adapter_id,
|
||||
MAX_ADAPTER_ID_SIZE,
|
||||
UTF16_LITTLE_ENDIAN,
|
||||
@ -406,6 +408,10 @@ kvp_send_key(struct work_struct *dummy)
|
||||
process_ib_ipinfo(in_msg, message, KVP_OP_SET_IP_INFO);
|
||||
break;
|
||||
case KVP_OP_GET_IP_INFO:
|
||||
/*
|
||||
* We only need to pass on the info of operation, adapter_id
|
||||
* and addr_family to the userland kvp daemon.
|
||||
*/
|
||||
process_ib_ipinfo(in_msg, message, KVP_OP_GET_IP_INFO);
|
||||
break;
|
||||
case KVP_OP_SET:
|
||||
@ -421,7 +427,7 @@ kvp_send_key(struct work_struct *dummy)
|
||||
UTF16_LITTLE_ENDIAN,
|
||||
message->body.kvp_set.data.value,
|
||||
HV_KVP_EXCHANGE_MAX_VALUE_SIZE - 1) + 1;
|
||||
break;
|
||||
break;
|
||||
|
||||
case REG_U32:
|
||||
/*
|
||||
@ -446,7 +452,10 @@ kvp_send_key(struct work_struct *dummy)
|
||||
break;
|
||||
|
||||
}
|
||||
case KVP_OP_GET:
|
||||
|
||||
/*
|
||||
* The key is always a string - utf16 encoding.
|
||||
*/
|
||||
message->body.kvp_set.data.key_size =
|
||||
utf16s_to_utf8s(
|
||||
(wchar_t *)in_msg->body.kvp_set.data.key,
|
||||
@ -454,7 +463,18 @@ kvp_send_key(struct work_struct *dummy)
|
||||
UTF16_LITTLE_ENDIAN,
|
||||
message->body.kvp_set.data.key,
|
||||
HV_KVP_EXCHANGE_MAX_KEY_SIZE - 1) + 1;
|
||||
break;
|
||||
|
||||
break;
|
||||
|
||||
case KVP_OP_GET:
|
||||
message->body.kvp_get.data.key_size =
|
||||
utf16s_to_utf8s(
|
||||
(wchar_t *)in_msg->body.kvp_get.data.key,
|
||||
in_msg->body.kvp_get.data.key_size,
|
||||
UTF16_LITTLE_ENDIAN,
|
||||
message->body.kvp_get.data.key,
|
||||
HV_KVP_EXCHANGE_MAX_KEY_SIZE - 1) + 1;
|
||||
break;
|
||||
|
||||
case KVP_OP_DELETE:
|
||||
message->body.kvp_delete.key_size =
|
||||
@ -464,12 +484,12 @@ kvp_send_key(struct work_struct *dummy)
|
||||
UTF16_LITTLE_ENDIAN,
|
||||
message->body.kvp_delete.key,
|
||||
HV_KVP_EXCHANGE_MAX_KEY_SIZE - 1) + 1;
|
||||
break;
|
||||
break;
|
||||
|
||||
case KVP_OP_ENUMERATE:
|
||||
message->body.kvp_enum_data.index =
|
||||
in_msg->body.kvp_enum_data.index;
|
||||
break;
|
||||
break;
|
||||
}
|
||||
|
||||
kvp_transaction.state = HVUTIL_USERSPACE_REQ;
|
||||
|
||||
@ -270,9 +270,11 @@ static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
|
||||
writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR);
|
||||
|
||||
/* send stop when last byte has been written */
|
||||
if (--dev->buf_len == 0)
|
||||
if (--dev->buf_len == 0) {
|
||||
if (!dev->use_alt_cmd)
|
||||
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
|
||||
at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_TXRDY);
|
||||
}
|
||||
|
||||
dev_dbg(dev->dev, "wrote 0x%x, to go %zu\n", *dev->buf, dev->buf_len);
|
||||
|
||||
@ -690,9 +692,8 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
|
||||
} else {
|
||||
at91_twi_write_next_byte(dev);
|
||||
at91_twi_write(dev, AT91_TWI_IER,
|
||||
AT91_TWI_TXCOMP |
|
||||
AT91_TWI_NACK |
|
||||
AT91_TWI_TXRDY);
|
||||
AT91_TWI_TXCOMP | AT91_TWI_NACK |
|
||||
(dev->buf_len ? AT91_TWI_TXRDY : 0));
|
||||
}
|
||||
}
|
||||
|
||||
@ -913,7 +914,7 @@ static struct at91_twi_pdata sama5d4_config = {
|
||||
|
||||
static struct at91_twi_pdata sama5d2_config = {
|
||||
.clk_max_div = 7,
|
||||
.clk_offset = 4,
|
||||
.clk_offset = 3,
|
||||
.has_unre_flag = true,
|
||||
.has_alt_cmd = true,
|
||||
.has_hold_field = true,
|
||||
|
||||
@ -115,6 +115,8 @@
|
||||
#define MAX_ADC_V2_CHANNELS 10
|
||||
#define MAX_ADC_V1_CHANNELS 8
|
||||
#define MAX_EXYNOS3250_ADC_CHANNELS 2
|
||||
#define MAX_EXYNOS4212_ADC_CHANNELS 4
|
||||
#define MAX_S5PV210_ADC_CHANNELS 10
|
||||
|
||||
/* Bit definitions common for ADC_V1 and ADC_V2 */
|
||||
#define ADC_CON_EN_START (1u << 0)
|
||||
@ -270,6 +272,19 @@ static void exynos_adc_v1_start_conv(struct exynos_adc *info,
|
||||
writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
|
||||
}
|
||||
|
||||
/* Exynos4212 and 4412 is like ADCv1 but with four channels only */
|
||||
static const struct exynos_adc_data exynos4212_adc_data = {
|
||||
.num_channels = MAX_EXYNOS4212_ADC_CHANNELS,
|
||||
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
|
||||
.needs_adc_phy = true,
|
||||
.phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
|
||||
|
||||
.init_hw = exynos_adc_v1_init_hw,
|
||||
.exit_hw = exynos_adc_v1_exit_hw,
|
||||
.clear_irq = exynos_adc_v1_clear_irq,
|
||||
.start_conv = exynos_adc_v1_start_conv,
|
||||
};
|
||||
|
||||
static const struct exynos_adc_data exynos_adc_v1_data = {
|
||||
.num_channels = MAX_ADC_V1_CHANNELS,
|
||||
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
|
||||
@ -282,6 +297,16 @@ static const struct exynos_adc_data exynos_adc_v1_data = {
|
||||
.start_conv = exynos_adc_v1_start_conv,
|
||||
};
|
||||
|
||||
static const struct exynos_adc_data exynos_adc_s5pv210_data = {
|
||||
.num_channels = MAX_S5PV210_ADC_CHANNELS,
|
||||
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
|
||||
|
||||
.init_hw = exynos_adc_v1_init_hw,
|
||||
.exit_hw = exynos_adc_v1_exit_hw,
|
||||
.clear_irq = exynos_adc_v1_clear_irq,
|
||||
.start_conv = exynos_adc_v1_start_conv,
|
||||
};
|
||||
|
||||
static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
|
||||
unsigned long addr)
|
||||
{
|
||||
@ -478,6 +503,12 @@ static const struct of_device_id exynos_adc_match[] = {
|
||||
}, {
|
||||
.compatible = "samsung,s3c6410-adc",
|
||||
.data = &exynos_adc_s3c64xx_data,
|
||||
}, {
|
||||
.compatible = "samsung,s5pv210-adc",
|
||||
.data = &exynos_adc_s5pv210_data,
|
||||
}, {
|
||||
.compatible = "samsung,exynos4212-adc",
|
||||
.data = &exynos4212_adc_data,
|
||||
}, {
|
||||
.compatible = "samsung,exynos-adc-v1",
|
||||
.data = &exynos_adc_v1_data,
|
||||
|
||||
@ -391,7 +391,7 @@ static int rcar_gyroadc_parse_subdevs(struct iio_dev *indio_dev)
|
||||
dev_err(dev,
|
||||
"Only %i channels supported with %s, but reg = <%i>.\n",
|
||||
num_channels, child->name, reg);
|
||||
return ret;
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
@ -400,7 +400,7 @@ static int rcar_gyroadc_parse_subdevs(struct iio_dev *indio_dev)
|
||||
dev_err(dev,
|
||||
"Channel %i uses different ADC mode than the rest.\n",
|
||||
reg);
|
||||
return ret;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Channel is valid, grab the regulator. */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user